src/mainboard/tyan/s4880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_PAYLOAD     = 1
  20
  21 ##
  22 ## Compute where this copy of coreboot will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up coreboot,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44 if HAVE_MP_TABLE object mptable.o end
  45 if HAVE_PIRQ_TABLE object irq_tables.o end
  46 if USE_DCACHE_RAM
  47
  48         if CONFIG_USE_INIT
  49
  50                 makerule ./auto.o
  51                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  52                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  53                 end
  54
  55         else
  56
  57                 makerule ./auto.inc
  58                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  59                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
  60                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  61                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  62                         end
  63         end
  64 else
  65
  66         ##
  67         ## Romcc output
  68         ##
  69         makerule ./failover.E
  70                 depends "$(MAINBOARD)/failover.c ../romcc"
  71                 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  72         end
  73
  74         makerule ./failover.inc
  75                 depends "$(MAINBOARD)/failover.c ../romcc"
  76                 action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  77         end
  78
  79         makerule ./auto.E
  80                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  81                 action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  82         end
  83
  84         makerule ./auto.inc
  85                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
  86                 action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  87         end
  88
  89         ##
  90         ## Setup RAM
  91         ##
  92         mainboardinit cpu/x86/fpu/enable_fpu.inc
  93         mainboardinit cpu/x86/mmx/enable_mmx.inc
  94         mainboardinit cpu/x86/sse/enable_sse.inc
  95         mainboardinit ./auto.inc
  96         mainboardinit cpu/x86/sse/disable_sse.inc
  97         mainboardinit cpu/x86/mmx/disable_mmx.inc
  98         mainboardinit arch/i386/lib/jmp_auto_out.inc
  99
 100 end
 101
 102 ##
 103 ## Build our 16 bit and 32 bit coreboot entry code
 104 ##
 105 if USE_FALLBACK_IMAGE
 106         mainboardinit cpu/x86/16bit/entry16.inc
 107         ldscript /cpu/x86/16bit/entry16.lds
 108 end
 109
 110 mainboardinit cpu/x86/32bit/entry32.inc
 111
 112 if USE_DCACHE_RAM
 113         if CONFIG_USE_INIT
 114                 ldscript /cpu/x86/32bit/entry32.lds
 115         end
 116
 117         if CONFIG_USE_INIT
 118                 ldscript /cpu/amd/car/cache_as_ram.lds
 119         end
 120 end
 121
 122
 123 ##
 124 ## Build our reset vector (This is where coreboot is entered)
 125 ##
 126 if USE_FALLBACK_IMAGE
 127         mainboardinit cpu/x86/16bit/reset16.inc
 128         ldscript /cpu/x86/16bit/reset16.lds
 129 else
 130         mainboardinit cpu/x86/32bit/reset32.inc
 131         ldscript /cpu/x86/32bit/reset32.lds
 132 end
 133
 134 if USE_DCACHE_RAM
 135 else
 136         ### Should this be in the northbridge code?
 137         mainboardinit arch/i386/lib/cpu_reset.inc
 138 end
 139
 140 ##
 141 ## Include an id string (For safe flashing)
 142 ##
 143 mainboardinit arch/i386/lib/id.inc
 144 ldscript /arch/i386/lib/id.lds
 145
 146
 147 if USE_DCACHE_RAM
 148         ##
 149         ## Setup Cache-As-Ram
 150         ##
 151         mainboardinit cpu/amd/car/cache_as_ram.inc
 152 end
 153
 154 ###
 155 ### This is the early phase of coreboot startup
 156 ### Things are delicate and we test to see if we should
 157 ### failover to another image.
 158 ###
 159 if USE_FALLBACK_IMAGE
 160         if USE_DCACHE_RAM
 161                 ldscript /arch/i386/lib/failover.lds
 162         else
 163                 ldscript /arch/i386/lib/failover.lds
 164                 mainboardinit ./failover.inc
 165         end
 166 end
 167
 168 ##
 169 ## Setup RAM
 170 ##
 171 if USE_DCACHE_RAM
 172
 173         if CONFIG_USE_INIT
 174                 initobject auto.o
 175         else
 176                 mainboardinit ./auto.inc
 177         end
 178
 179 else
 180
 181         # ROMCC
 182         mainboardinit arch/i386/lib/jmp_auto.inc
 183
 184 end
 185
 186 ##
 187 ## Include the secondary Configuration files
 188 ##
 189 config chip.h
 190
 191 # sample config for tyan/s4880
 192 chip northbridge/amd/amdk8/root_complex
 193         device apic_cluster 0 on
 194                 chip cpu/amd/socket_940
 195                         device apic 0 on end
 196                 end
 197         end
 198
 199         device pci_domain 0 on
 200                 chip northbridge/amd/amdk8
 201                         device pci 18.0 on end # LDT0
 202                         device pci 18.0 on end # LDT1
 203                         device pci 18.0 on #  northbridge
 204                                 #  devices on link 2, link 2 == LDT 2
 205                                 chip southbridge/amd/amd8131
 206                                         # the on/off keyword is mandatory
 207                                         device pci 0.0 on
 208 #                                                chip drivers/lsi/53c1030
 209 #                                                        device pci 4.0 on end
 210 #                                                        device pci 4.1 on end
 211 #                                                        register "fw_address" = "0xfff8c000"
 212 #                                                end
 213                                                 chip drivers/pci/onboard
 214                                                         device pci 9.0 on end
 215                                                         device pci 9.1 on end
 216                                                 end
 217                                         end
 218                                         device pci 0.1 on end
 219                                         device pci 1.0 on end
 220                                         device pci 1.1 on end
 221                                 end
 222                                 chip southbridge/amd/amd8111
 223                                         # this "device pci 0.0" is the parent the next one
 224                                         # PCI bridge
 225                                         device pci 0.0 on
 226                                                 device pci 0.0 on end
 227                                                 device pci 0.1 on end
 228                                                 device pci 0.2 off end
 229                                                 device pci 1.0 off end
 230                                                 chip drivers/pci/onboard
 231                                                         device pci 6.0 on end
 232                                                         register "rom_address" = "0xfff80000"
 233                                                 end
 234                                         end
 235                                         device pci 1.0 on
 236                                                 chip superio/winbond/w83627hf
 237                                                         device pnp 2e.0 on #  Floppy
 238                                                                 io 0x60 = 0x3f0
 239                                                                 irq 0x70 = 6
 240                                                                 drq 0x74 = 2
 241                                                         end
 242                                                         device pnp 2e.1 off #  Parallel Port
 243                                                                 io 0x60 = 0x378
 244                                                                 irq 0x70 = 7
 245                                                         end
 246                                                         device pnp 2e.2 on #  Com1
 247                                                                 io 0x60 = 0x3f8
 248                                                                 irq 0x70 = 4
 249                                                         end
 250                                                         device pnp 2e.3 off #  Com2
 251                                                                 io 0x60 = 0x2f8
 252                                                                 irq 0x70 = 3
 253                                                         end
 254                                                         device pnp 2e.5 on #  Keyboard
 255                                                                 io 0x60 = 0x60
 256                                                                 io 0x62 = 0x64
 257                                                                 irq 0x70 = 1
 258                                                                 irq 0x72 = 12
 259                                                         end
 260                                                         device pnp 2e.6 off #  CIR
 261                                                                 io 0x60 = 0x100
 262                                                         end
 263                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 264                                                                 io 0x60 = 0x220
 265                                                                 io 0x62 = 0x300
 266                                                                 irq 0x70 = 9
 267                                                         end
 268                                                         device pnp 2e.8 off end #  GPIO2
 269                                                         device pnp 2e.9 off end #  GPIO3
 270                                                         device pnp 2e.a off end #  ACPI
 271                                                         device pnp 2e.b on #  HW Monitor
 272                                                                 io 0x60 = 0x290
 273                                                                 irq 0x70 = 5
 274                                                         end
 275                                                 end
 276                                         end
 277                                         device pci 1.1 on end
 278                                         device pci 1.2 on end
 279                                         device pci 1.3 on end
 280                                         device pci 1.5 off end
 281                                         device pci 1.6 off end
 282                                         register "ide0_enable" = "1"
 283                                         register "ide1_enable" = "1"
 284                                 end
 285                         end #  device pci 18.0
 286
 287                         device pci 18.1 on end
 288                         device pci 18.2 on end
 289                         device pci 18.3 on end
 290                 end
 291
 292         end #pci_domain
 293 end
 294