2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define RAMINIT_SYSINFO 1
24 #define FAM10_SCAN_PCI_BUS 0
25 #define FAM10_ALLOCATE_IO_RANGE 1
27 #define QRANK_DIMM_SUPPORT 1
29 #if CONFIG_LOGICAL_CPUS==1
30 #define SET_NB_CFG_54 1
34 #define SET_FIDVID_CORE_RANGE 0
38 #include <device/pci_def.h>
39 #include <device/pci_ids.h>
41 #include <device/pnp_def.h>
42 #include <arch/romcc_io.h>
43 #include <cpu/x86/lapic.h>
44 #include <console/console.h>
46 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
47 #include "pc80/usbdebug_serial.c"
51 #include <cpu/amd/model_10xxx_rev.h>
53 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
54 #include "northbridge/amd/amdfam10/raminit.h"
55 #include "northbridge/amd/amdfam10/amdfam10.h"
57 #include "cpu/amd/model_10xxx/apic_timer.c"
58 #include "lib/delay.c"
59 #include "cpu/x86/lapic/boot_cpu.c"
60 #include "northbridge/amd/amdfam10/reset_test.c"
61 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
62 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
64 #include "cpu/x86/bist.h"
66 #include "northbridge/amd/amdfam10/debug.c"
68 #include "cpu/x86/mtrr/earlymtrr.c"
70 #include "northbridge/amd/amdfam10/setup_resource_map.c"
72 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
74 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
81 static inline int spd_read_byte(unsigned device, unsigned address)
83 return smbus_read_byte(device, address);
86 #include "northbridge/amd/amdfam10/amdfam10.h"
88 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
89 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
91 #include "resourcemap.c"
93 #include "cpu/amd/quadcore/quadcore.c"
96 #define MCP55_USE_NIC 1
98 #define MCP55_PCI_E_X_0 1
100 #define MCP55_MB_SETUP \
101 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
102 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
103 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
104 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
105 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
106 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
108 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
109 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
111 #include "cpu/amd/car/post_cache_as_ram.c"
113 #include "cpu/amd/microcode/microcode.c"
114 #include "cpu/amd/model_10xxx/update_microcode.c"
115 #include "cpu/amd/model_10xxx/init_cpus.c"
118 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
119 #include "northbridge/amd/amdfam10/early_ht.c"
121 static void sio_setup(void)
126 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
128 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
130 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
133 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
135 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
137 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
140 #include "spd_addr.h"
142 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
144 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
151 if (!cpu_init_detectedx && boot_cpu()) {
152 /* Nothing special needs to be done to find bus 0 */
153 /* Allow the HT devices to be found */
155 set_bsp_node_CHtExtNodeCfgEn();
156 enumerate_ht_chain();
160 /* Setup the mcp55 */
167 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
172 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
175 printk(BIOS_DEBUG, "\n");
177 /* Halt if there was a built in self test failure */
178 report_bist_failure(bist);
181 mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
182 early_usbdebug_init();
186 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
187 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
188 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
189 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
191 /* Setup sysinfo defaults */
192 set_sysinfo_in_ram(0);
194 update_microcode(val);
200 amd_ht_init(sysinfo);
203 /* Setup nodes PCI space and start core 0 AP init. */
204 finalize_node_setup(sysinfo);
206 /* Setup any mainboard PCI settings etc. */
207 setup_mb_resource_map();
210 /* wait for all the APs core0 started by finalize_node_setup. */
211 /* FIXME: A bunch of cores are going to start output to serial at once.
212 * It would be nice to fixup prink spinlocks for ROM XIP mode.
213 * I think it could be done by putting the spinlock flag in the cache
214 * of the BSP located right after sysinfo.
216 wait_all_core0_started();
218 #if CONFIG_LOGICAL_CPUS==1
219 /* Core0 on each node is configured. Now setup any additional cores. */
220 printk(BIOS_DEBUG, "start_other_cores()\n");
223 wait_all_other_cores_started(bsp_apicid);
229 msr = rdmsr(0xc0010071);
230 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
232 /* FIXME: The sb fid change may survive the warm reset and only
233 * need to be done once.*/
234 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
238 if (!warm_reset_detect(0)) { // BSP is node 0
239 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
241 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
246 /* show final fid and vid */
247 msr=rdmsr(0xc0010071);
248 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
251 init_timer(); // Need to use TMICT to synconize FID/VID
253 wants_reset = mcp55_early_setup_x();
255 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
256 if (!warm_reset_detect(0)) {
257 print_info("...WARM RESET...\n\n\n");
259 die("After soft_reset_x - shouldn't see this message!!!\n");
263 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
267 /* It's the time to set ctrl in sysinfo now; */
268 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
269 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
272 printk(BIOS_DEBUG, "enable_smbus()\n");
277 printk(BIOS_DEBUG, "raminit_amdmct()\n");
278 raminit_amdmct(sysinfo);
281 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
282 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
283 post_code(0x43); // Should never see this post code.