2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_HAVE_MP_TABLE
24 uses CONFIG_HAVE_PIRQ_TABLE
25 uses CONFIG_HAVE_ACPI_TABLES
26 uses CONFIG_HAVE_ACPI_RESUME
27 uses CONFIG_ACPI_SSDTX_NUM
28 uses CONFIG_USE_FALLBACK_IMAGE
29 uses CONFIG_USE_FAILOVER_IMAGE
30 uses CONFIG_HAVE_FALLBACK_BOOT
31 uses CONFIG_HAVE_FAILOVER_BOOT
32 uses CONFIG_HAVE_HARD_RESET
33 uses CONFIG_IRQ_SLOT_COUNT
34 uses CONFIG_HAVE_OPTION_TABLE
36 uses CONFIG_MAX_PHYSICAL_CPUS
37 uses CONFIG_LOGICAL_CPUS
40 uses CONFIG_FALLBACK_SIZE
41 uses CONFIG_FAILOVER_SIZE
43 uses CONFIG_ROM_SECTION_SIZE
44 uses CONFIG_ROM_IMAGE_SIZE
45 uses CONFIG_ROM_SECTION_SIZE
46 uses CONFIG_ROM_SECTION_OFFSET
47 uses CONFIG_ROM_PAYLOAD
48 uses CONFIG_ROM_PAYLOAD_START
49 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
50 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
51 uses CONFIG_PAYLOAD_SIZE
53 uses CONFIG_XIP_ROM_SIZE
54 uses CONFIG_XIP_ROM_BASE
55 uses CONFIG_STACK_SIZE
57 uses CONFIG_USE_OPTION_TABLE
58 uses CONFIG_LB_CKS_RANGE_START
59 uses CONFIG_LB_CKS_RANGE_END
60 uses CONFIG_LB_CKS_LOC
61 uses CONFIG_MAINBOARD_PART_NUMBER
62 uses CONFIG_MAINBOARD_VENDOR
64 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
65 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
66 uses COREBOOT_EXTRA_VERSION
68 uses CONFIG_TTYS0_BAUD
69 uses CONFIG_TTYS0_BASE
71 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
72 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
73 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 uses CONFIG_CONSOLE_SERIAL8250
75 uses CONFIG_HAVE_INIT_TIMER
78 uses CONFIG_CROSS_COMPILE
82 uses CONFIG_CONSOLE_VGA
83 uses CONFIG_USBDEBUG_DIRECT
84 uses CONFIG_PCI_ROM_RUN
85 uses CONFIG_HW_MEM_HOLE_SIZEK
86 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
88 uses CONFIG_HT_CHAIN_UNITID_BASE
89 uses CONFIG_HT_CHAIN_END_UNITID_BASE
90 uses CONFIG_SB_HT_CHAIN_ON_BUS0
91 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
93 uses CONFIG_USE_DCACHE_RAM
94 uses CONFIG_DCACHE_RAM_BASE
95 uses CONFIG_DCACHE_RAM_SIZE
96 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
99 uses CONFIG_SERIAL_CPU_INIT
101 uses CONFIG_ENABLE_APIC_EXT_ID
102 uses CONFIG_APIC_ID_OFFSET
103 uses CONFIG_LIFT_BSP_APIC_ID
105 uses CONFIG_PCI_64BIT_PREF_MEM
107 uses CONFIG_LB_MEM_TOPK
109 uses CONFIG_PCI_BUS_SEGN_BITS
111 uses CONFIG_AP_CODE_IN_CAR
113 uses CONFIG_MEM_TRAIN_SEQ
115 uses CONFIG_WAIT_BEFORE_CPUS_INIT
119 uses CONFIG_USE_PRINTK_IN_CAR
120 uses CONFIG_CAR_FAM10
121 uses CONFIG_AMD_UCODE_PATCH_FILE
128 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
130 default CONFIG_ROM_SIZE=1024*1024
131 #default CONFIG_ROM_SIZE=0x100000
134 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
136 #default CONFIG_FALLBACK_SIZE=131072
137 #default CONFIG_FALLBACK_SIZE=0x40000
139 default CONFIG_FALLBACK_SIZE=0x3f000
140 default CONFIG_FAILOVER_SIZE=0x01000
143 default CONFIG_LB_MEM_TOPK=16384
146 ## Build code for the fallback boot
148 default CONFIG_HAVE_FALLBACK_BOOT=1
149 default CONFIG_HAVE_FAILOVER_BOOT=1
152 ## Build code to reset the motherboard from coreboot
154 default CONFIG_HAVE_HARD_RESET=1
157 ## Build code to export a programmable irq routing table
159 default CONFIG_HAVE_PIRQ_TABLE=1
160 default CONFIG_IRQ_SLOT_COUNT=11
163 ## Build code to export an x86 MP table
164 ## Useful for specifying IRQ routing values
166 default CONFIG_HAVE_MP_TABLE=1
168 ## ACPI tables will be included
169 default CONFIG_HAVE_ACPI_TABLES=0
171 default CONFIG_ACPI_SSDTX_NUM=31
174 ## Build code to export a CMOS option table
176 default CONFIG_HAVE_OPTION_TABLE=1
179 ## Move the default coreboot cmos range off of AMD RTC registers
181 default CONFIG_LB_CKS_RANGE_START=49
182 default CONFIG_LB_CKS_RANGE_END=122
183 default CONFIG_LB_CKS_LOC=123
186 ## Build code for SMP support
187 ## Only worry about 2 micro processors
190 default CONFIG_MAX_PHYSICAL_CPUS=2
191 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
192 default CONFIG_LOGICAL_CPUS=1
194 #default CONFIG_SERIAL_CPU_INIT=0
196 default CONFIG_ENABLE_APIC_EXT_ID=1
197 default CONFIG_APIC_ID_OFFSET=0x00
198 default CONFIG_LIFT_BSP_APIC_ID=1
200 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
202 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
204 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
206 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
208 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
209 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
212 default CONFIG_CONSOLE_VGA=1
213 default CONFIG_PCI_ROM_RUN=1
215 #default CONFIG_USBDEBUG_DIRECT=1
217 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
218 default CONFIG_HT_CHAIN_UNITID_BASE=1
220 #real SB Unit ID, default is 0x20, mean dont touch it at last
221 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
223 #make the SB HT chain on bus 0, default is not (0)
224 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
226 #only offset for SB chain?, default is yes(1)
227 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
229 #allow capable device use that above 4G
230 #default CONFIG_PCI_64BIT_PREF_MEM=1
233 ## enable CACHE_AS_RAM specifics
235 default CONFIG_USE_DCACHE_RAM=1
236 default CONFIG_DCACHE_RAM_BASE=0xc4000
237 default CONFIG_DCACHE_RAM_SIZE=0x0c000
238 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
239 default CONFIG_USE_INIT=0
241 default CONFIG_MEM_TRAIN_SEQ=2
242 default CONFIG_WAIT_BEFORE_CPUS_INIT=0
243 default CONFIG_AMDMCT = 1
246 ## Build code to setup a generic IOAPIC
248 default CONFIG_IOAPIC=1
251 ## Clean up the motherboard id strings
253 default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)"
254 default CONFIG_MAINBOARD_VENDOR="Tyan"
255 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
256 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
259 ## Set microcode patch file name
261 ## Barcelona rev DR-Ax: "mc_patch_01000020.h"
262 ## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
263 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
264 ## Shanghai rev DA-C2: "mc_patch_0100009f.h"
266 default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
269 ### coreboot layout values
272 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
273 default CONFIG_ROM_IMAGE_SIZE = 65536
276 ## Use a small 8K stack
278 default CONFIG_STACK_SIZE=0x2000
281 ## Use a small 32K heap
283 default CONFIG_HEAP_SIZE=0xc0000
286 ## Only use the option table in a normal image
288 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
291 ## Coreboot C code runs at this location in RAM
293 default CONFIG_RAMBASE=0x00200000
296 ## Load the payload from the ROM
298 default CONFIG_ROM_PAYLOAD = 1
300 #default CONFIG_COMPRESSED_PAYLOAD = 1
303 ### Defaults of options that you may want to override in the target config file
307 ## The default compiler
309 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
310 default CONFIG_HOSTCC="gcc"
313 ## Disable the gdb stub by default
315 default CONFIG_GDB_STUB=0
318 ## The Serial Console
320 default CONFIG_USE_PRINTK_IN_CAR=1
322 # To Enable the Serial Console
323 default CONFIG_CONSOLE_SERIAL8250=1
325 ## Select the serial console baud rate
326 default CONFIG_TTYS0_BAUD=115200
327 #default CONFIG_TTYS0_BAUD=57600
328 #default CONFIG_TTYS0_BAUD=38400
329 #default CONFIG_TTYS0_BAUD=19200
330 #default CONFIG_TTYS0_BAUD=9600
331 #default CONFIG_TTYS0_BAUD=4800
332 #default CONFIG_TTYS0_BAUD=2400
333 #default CONFIG_TTYS0_BAUD=1200
335 # Select the serial console base port
336 default CONFIG_TTYS0_BASE=0x3f8
338 # Select the serial protocol
339 # This defaults to 8 data bits, 1 stop bit, and no parity
340 default CONFIG_TTYS0_LCS=0x3
343 ### Select the coreboot loglevel
345 ## EMERG 1 system is unusable
346 ## ALERT 2 action must be taken immediately
347 ## CRIT 3 critical conditions
348 ## ERR 4 error conditions
349 ## WARNING 5 warning conditions
350 ## NOTICE 6 normal but significant condition
351 ## INFO 7 informational
352 ## CONFIG_DEBUG 8 debug-level messages
353 ## SPEW 9 Way too many details
355 ## Request this level of debugging output
356 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
357 ## At a maximum only compile in this level of debugging
358 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
361 ## Select power on after power fail setting
362 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
369 default CONFIG_CBFS=0