src/mainboard/tyan/s2895/romstage.c

   1 #define K8_ALLOCATE_IO_RANGE 1
   2
   3 #define QRANK_DIMM_SUPPORT 1
   4
   5 #if CONFIG_LOGICAL_CPUS==1
   6 #define SET_NB_CFG_54 1
   7 #endif
   8
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <device/pci_def.h>
  12 #include <arch/io.h>
  13 #include <device/pnp_def.h>
  14 #include <arch/romcc_io.h>
  15 #include <cpu/x86/lapic.h>
  16 #include "option_table.h"
  17 #include "pc80/mc146818rtc_early.c"
  18 #include <console/console.h>
  19 #include "lib/ramtest.c"
  20 #include <cpu/amd/model_fxx_rev.h>
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  23 #include "northbridge/amd/amdk8/raminit.h"
  24 #include "cpu/amd/model_fxx/apic_timer.c"
  25 #include "lib/delay.c"
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/amd/amdk8/reset_test.c"
  28 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  29 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  30 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  31 #define SUPERIO_GPIO_IO_BASE 0x400
  32 #include "cpu/x86/bist.h"
  33 #include "northbridge/amd/amdk8/debug.c"
  34 #include <cpu/amd/mtrr.h>
  35 #include "cpu/x86/mtrr/earlymtrr.c"
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  38
  39 static void memreset_setup(void)
  40 {
  41 }
  42
  43 static void memreset(int controllers, const struct mem_controller *ctrl)
  44 {
  45 }
  46
  47 static void sio_gpio_setup(void)
  48 {
  49         unsigned value;
  50
  51         /*Enable onboard scsi*/
  52         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  53         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  54         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  55 }
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67 #include "northbridge/amd/amdk8/raminit.c"
  68 #include "northbridge/amd/amdk8/coherent_ht.c"
  69 #include "lib/generic_sdram.c"
  70
  71  /* tyan does not want the default */
  72 #include "resourcemap.c"
  73
  74 #include "cpu/amd/dualcore/dualcore.c"
  75
  76 #define CK804_NUM 2
  77 #define CK804_USE_NIC 1
  78 #define CK804_USE_ACI 1
  79
  80 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  81
  82 //set GPIO to input mode
  83 #define CK804_MB_SETUP \
  84         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  85         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  86         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  87         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  88         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  89         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  90
  91 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  92
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  99 #include "northbridge/amd/amdk8/early_ht.c"
 100
 101 static void sio_setup(void)
 102 {
 103         unsigned value;
 104         u32 dword;
 105         u8 byte;
 106
 107         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 108
 109         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 110         byte |= 0x20;
 111         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 112
 113         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 114         dword |= (1<<29)|(1<<0);
 115         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 116
 117         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 118         dword |= (1<<16);
 119         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 120
 121         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 122         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 123         value &= 0xbf;
 124         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 125 }
 126
 127 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 128 {
 129         static const u16 spd_addr [] = {
 130                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 131                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 132                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 133                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 134         };
 135
 136         int needs_reset;
 137         unsigned bsp_apicid = 0;
 138
 139         struct mem_controller ctrl[8];
 140         unsigned nodes;
 141
 142         if (!cpu_init_detectedx && boot_cpu()) {
 143                 /* Nothing special needs to be done to find bus 0 */
 144                 /* Allow the HT devices to be found */
 145
 146                 enumerate_ht_chain();
 147
 148                 sio_setup();
 149
 150                 /* Setup the ck804 */
 151                 ck804_enable_rom();
 152         }
 153
 154         if (bist == 0) {
 155                 bsp_apicid = init_cpus(cpu_init_detectedx);
 156         }
 157
 158         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 159         uart_init();
 160         console_init();
 161
 162         /* Halt if there was a built in self test failure */
 163         report_bist_failure(bist);
 164
 165         sio_gpio_setup();
 166
 167         setup_mb_resource_map();
 168
 169         needs_reset = setup_coherent_ht_domain();
 170
 171         wait_all_core0_started();
 172
 173         // It is said that we should start core1 after all core0 launched
 174         start_other_cores();
 175         wait_all_other_cores_started(bsp_apicid);
 176
 177         needs_reset |= ht_setup_chains_x();
 178
 179         needs_reset |= ck804_early_setup_x();
 180
 181         if (needs_reset) {
 182                 printk(BIOS_INFO, "ht reset -\n");
 183                 soft_reset();
 184         }
 185
 186         allow_all_aps_stop(bsp_apicid);
 187
 188         nodes = get_nodes();
 189         //It's the time to set ctrl now;
 190         fill_mem_ctrl(nodes, ctrl, spd_addr);
 191
 192         enable_smbus();
 193
 194         memreset_setup();
 195         sdram_initialize(nodes, ctrl);
 196
 197         post_cache_as_ram();
 198 }
 199