1 #define K8_ALLOCATE_IO_RANGE 1
3 #define QRANK_DIMM_SUPPORT 1
5 #if CONFIG_LOGICAL_CPUS==1
6 #define SET_NB_CFG_54 1
11 #include <device/pci_def.h>
13 #include <device/pnp_def.h>
14 #include <arch/romcc_io.h>
15 #include <cpu/x86/lapic.h>
16 #include <pc80/mc146818rtc.h>
17 #include <console/console.h>
19 #include <cpu/amd/model_fxx_rev.h>
20 #include "northbridge/amd/amdk8/incoherent_ht.c"
21 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
22 #include "northbridge/amd/amdk8/raminit.h"
23 #include "cpu/amd/model_fxx/apic_timer.c"
24 #include "lib/delay.c"
25 #include "cpu/x86/lapic/boot_cpu.c"
26 #include "northbridge/amd/amdk8/reset_test.c"
27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
28 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
29 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
30 #define SUPERIO_GPIO_IO_BASE 0x400
31 #include "cpu/x86/bist.h"
32 #include "northbridge/amd/amdk8/debug.c"
33 #include <cpu/amd/mtrr.h>
34 #include "cpu/x86/mtrr/earlymtrr.c"
35 #include "northbridge/amd/amdk8/setup_resource_map.c"
36 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
38 static void memreset_setup(void)
42 static void memreset(int controllers, const struct mem_controller *ctrl)
46 static void sio_gpio_setup(void)
50 /*Enable onboard scsi*/
51 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
52 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
53 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
61 static inline int spd_read_byte(unsigned device, unsigned address)
63 return smbus_read_byte(device, address);
66 #include "northbridge/amd/amdk8/raminit.c"
67 #include "northbridge/amd/amdk8/coherent_ht.c"
68 #include "lib/generic_sdram.c"
70 /* tyan does not want the default */
71 #include "resourcemap.c"
73 #include "cpu/amd/dualcore/dualcore.c"
75 #define CK804_USE_NIC 1
76 #define CK804_USE_ACI 1
78 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
80 //set GPIO to input mode
81 #define CK804_MB_SETUP \
82 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
83 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
84 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
85 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
86 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
87 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
89 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
91 #include "cpu/amd/car/post_cache_as_ram.c"
93 #include "cpu/amd/model_fxx/init_cpus.c"
95 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
96 #include "northbridge/amd/amdk8/early_ht.c"
98 static void sio_setup(void)
104 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
106 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
108 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
110 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
111 dword |= (1<<29)|(1<<0);
112 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
114 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
116 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
118 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
119 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
121 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
124 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
126 static const u16 spd_addr [] = {
127 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
128 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
129 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
130 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
134 unsigned bsp_apicid = 0;
136 struct mem_controller ctrl[8];
139 if (!cpu_init_detectedx && boot_cpu()) {
140 /* Nothing special needs to be done to find bus 0 */
141 /* Allow the HT devices to be found */
143 enumerate_ht_chain();
147 /* Setup the ck804 */
152 bsp_apicid = init_cpus(cpu_init_detectedx);
155 lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
159 /* Halt if there was a built in self test failure */
160 report_bist_failure(bist);
164 setup_mb_resource_map();
166 needs_reset = setup_coherent_ht_domain();
168 wait_all_core0_started();
170 // It is said that we should start core1 after all core0 launched
172 wait_all_other_cores_started(bsp_apicid);
174 needs_reset |= ht_setup_chains_x();
176 needs_reset |= ck804_early_setup_x();
179 printk(BIOS_INFO, "ht reset -\n");
183 allow_all_aps_stop(bsp_apicid);
186 //It's the time to set ctrl now;
187 fill_mem_ctrl(nodes, ctrl, spd_addr);
192 sdram_initialize(nodes, ctrl);