src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include "northbridge/amd/amdk8/cpu_rev.c"
  17 #define K8_HT_FREQ_1G_SUPPORT 1
  18 #define K8_ALLOCATE_IO_RANGE 1
  19 //#define K8_SCAN_PCI_BUS 1
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25
  26 #if CONFIG_USE_INIT == 0
  27 #include "lib/memcpy.c"
  28 #endif
  29
  30 #include "cpu/x86/lapic/boot_cpu.c"
  31 #include "northbridge/amd/amdk8/reset_test.c"
  32 #include "northbridge/amd/amdk8/debug.c"
  33 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  34
  35 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  36 #include "cpu/x86/bist.h"
  37
  38 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  39
  40 #include "northbridge/amd/amdk8/setup_resource_map.c"
  41
  42 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  43
  44 static void hard_reset(void)
  45 {
  46         set_bios_reset();
  47
  48         /* full reset */
  49         outb(0x0a, 0x0cf9);
  50         outb(0x0e, 0x0cf9);
  51 }
  52
  53 static void soft_reset(void)
  54 {
  55         set_bios_reset();
  56 #if 1
  57         /* link reset */
  58         outb(0x02, 0x0cf9);
  59         outb(0x06, 0x0cf9);
  60 #endif
  61 }
  62
  63 static void memreset_setup(void)
  64 {
  65 }
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69 }
  70
  71 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  72
  73 #define SUPERIO_GPIO_IO_BASE 0x400
  74
  75 static void sio_gpio_setup(void){
  76
  77         unsigned value;
  78
  79 //      lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
  80
  81         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  82         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  83         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  84
  85 }
  86
  87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  88 {
  89         /* nothing to do */
  90 }
  91
  92 static inline int spd_read_byte(unsigned device, unsigned address)
  93 {
  94         return smbus_read_byte(device, address);
  95 }
  96
  97 #define K8_4RANK_DIMM_SUPPORT 1
  98
  99 #include "northbridge/amd/amdk8/raminit.c"
 100 #if 0
 101         #define ENABLE_APIC_EXT_ID 1
 102         #define APIC_ID_OFFSET 0x10
 103         #define LIFT_BSP_APIC_ID 0
 104 #else
 105         #define ENABLE_APIC_EXT_ID 0
 106 #endif
 107 #include "northbridge/amd/amdk8/coherent_ht.c"
 108 #include "sdram/generic_sdram.c"
 109
 110  /* tyan does not want the default */
 111 #include "resourcemap.c"
 112
 113 #if CONFIG_LOGICAL_CPUS==1
 114 #define SET_NB_CFG_54 1
 115 #include "cpu/amd/dualcore/dualcore.c"
 116 #else
 117 #include "cpu/amd/model_fxx/node_id.c"
 118 #endif
 119
 120 #define FIRST_CPU  1
 121 #define SECOND_CPU 1
 122 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 123
 124 #define CK804_NUM 2
 125 #define CK804B_BUSN 0x80
 126 #define CK804_USE_NIC 1
 127 #define CK804_USE_ACI 1
 128
 129 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 130
 131 //set GPIO to input mode
 132 #define CK804_MB_SETUP \
 133                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 134                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 135                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 136                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 137                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 138                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 139
 140 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 141
 142 #include "cpu/amd/car/copy_and_run.c"
 143
 144 #if USE_FALLBACK_IMAGE == 1
 145
 146 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 147 #include "northbridge/amd/amdk8/early_ht.c"
 148
 149
 150 static void sio_setup(void)
 151 {
 152
 153         unsigned value;
 154         uint32_t dword;
 155         uint8_t byte;
 156
 157
 158         /* LPC Variable Range Decode 1 0x400-0x47f */
 159         /* to make sure lpc47b397 gpio on device work */
 160         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 161
 162         /* subject decoding*/
 163         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 164         byte |= 0x20;
 165         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 166
 167         /* LPC Positive Decode 0 */
 168         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 169         /*decode VAR1, serial 0 */
 170         dword |= (1<<29)|(1<<0);
 171         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 172
 173 #if  1
 174         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 175
 176         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 177         value &= 0xbf;
 178         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 179 #endif
 180
 181 }
 182
 183 void real_main(unsigned long bist);
 184
 185 void amd64_main(unsigned long bist)
 186 {
 187 #if CONFIG_LOGICAL_CPUS==1
 188         struct node_core_id id;
 189 #else
 190         unsigned nodeid;
 191 #endif
 192         /* Make cerain my local apic is useable */
 193 //        enable_lapic();
 194
 195 #if CONFIG_LOGICAL_CPUS==1
 196         id = get_node_core_id_x();
 197         /* Is this a cpu only reset? */
 198         if (cpu_init_detected(id.nodeid)) {
 199 #else
 200 //        nodeid = lapicid() & 0xf;
 201         nodeid = get_node_id();
 202         /* Is this a cpu only reset? */
 203         if (cpu_init_detected(nodeid)) {
 204 #endif
 205                 if (last_boot_normal()) {
 206                         goto normal_image;
 207                 } else {
 208                         goto cpu_reset;
 209                 }
 210         }
 211
 212         /* Is this a secondary cpu? */
 213         if (!boot_cpu()) {
 214                 if (last_boot_normal()) {
 215                         goto normal_image;
 216                 } else {
 217                         goto fallback_image;
 218                 }
 219         }
 220
 221         /* Nothing special needs to be done to find bus 0 */
 222         /* Allow the HT devices to be found */
 223
 224         enumerate_ht_chain();
 225
 226         sio_setup();
 227
 228         /* Setup the ck804 */
 229         ck804_enable_rom();
 230
 231         /* Is this a deliberate reset by the bios */
 232         if (bios_reset_detected() && last_boot_normal()) {
 233                 goto normal_image;
 234         }
 235         /* This is the primary cpu how should I boot? */
 236         else if (do_normal_boot()) {
 237                 goto normal_image;
 238         }
 239         else {
 240                 goto fallback_image;
 241         }
 242  normal_image:
 243         __asm__ volatile ("jmp __normal_image"
 244                 : /* outputs */
 245                 : "a" (bist) /* inputs */
 246                 );
 247  cpu_reset:
 248 #if 0
 249         //CPU reset will reset memtroller ???
 250         asm volatile ("jmp __cpu_reset"
 251                 : /* outputs */
 252                 : "a"(bist) /* inputs */
 253                 );
 254 #endif
 255
 256  fallback_image:
 257         real_main(bist);
 258 }
 259 void real_main(unsigned long bist)
 260 #else
 261 void amd64_main(unsigned long bist)
 262 #endif
 263 {
 264         static const struct mem_controller cpu[] = {
 265 #if FIRST_CPU
 266                 {
 267                         .node_id = 0,
 268                         .f0 = PCI_DEV(0, 0x18, 0),
 269                         .f1 = PCI_DEV(0, 0x18, 1),
 270                         .f2 = PCI_DEV(0, 0x18, 2),
 271                         .f3 = PCI_DEV(0, 0x18, 3),
 272                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 273                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 274                 },
 275 #endif
 276 #if SECOND_CPU
 277                 {
 278                         .node_id = 1,
 279                         .f0 = PCI_DEV(0, 0x19, 0),
 280                         .f1 = PCI_DEV(0, 0x19, 1),
 281                         .f2 = PCI_DEV(0, 0x19, 2),
 282                         .f3 = PCI_DEV(0, 0x19, 3),
 283                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 284                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 285                 },
 286 #endif
 287         };
 288
 289         int needs_reset;
 290
 291         unsigned cpu_reset = 0;
 292
 293         if (bist == 0) {
 294 #if CONFIG_LOGICAL_CPUS==1
 295                 struct node_core_id id;
 296 #else
 297                 unsigned nodeid;
 298 #endif
 299                 /* Skip this if there was a built in self test failure */
 300 //                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
 301
 302 #if CONFIG_LOGICAL_CPUS==1
 303                 set_apicid_cpuid_lo();
 304                 id = get_node_core_id_x(); // that is initid
 305         #if ENABLE_APIC_EXT_ID == 1
 306                 if(id.coreid == 0) {
 307                         enable_apic_ext_id(id.nodeid);
 308                 }
 309         #endif
 310 #else
 311                 nodeid = get_node_id();
 312         #if ENABLE_APIC_EXT_ID == 1
 313                 enable_apic_ext_id(nodeid);
 314         #endif
 315 #endif
 316
 317                 enable_lapic();
 318
 319 //                init_timer();
 320
 321
 322 #if CONFIG_LOGICAL_CPUS==1
 323         #if ENABLE_APIC_EXT_ID == 1
 324             #if LIFT_BSP_APIC_ID == 0
 325                 if( id.nodeid != 0 ) //all except cores in node0
 326             #endif
 327                         lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
 328         #endif
 329                 if(id.coreid == 0) {
 330                         if (cpu_init_detected(id.nodeid)) {
 331 //                                __asm__ volatile ("jmp __cpu_reset");
 332                                 cpu_reset = 1;
 333                                 goto cpu_reset_x;
 334                         }
 335                         distinguish_cpu_resets(id.nodeid);
 336 //                        start_other_core(id.nodeid);
 337                 }
 338 #else
 339         #if ENABLE_APIC_EXT_ID == 1
 340             #if LIFT_BSP_APIC_ID == 0
 341                 if(nodeid != 0)
 342             #endif
 343                         lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
 344
 345         #endif
 346                 if (cpu_init_detected(nodeid)) {
 347 //                                __asm__ volatile ("jmp __cpu_reset");
 348                                 cpu_reset = 1;
 349                                 goto cpu_reset_x;
 350                 }
 351                 distinguish_cpu_resets(nodeid);
 352 #endif
 353
 354
 355                 if (!boot_cpu()
 356 #if CONFIG_LOGICAL_CPUS==1
 357                         || (id.coreid != 0)
 358 #endif
 359                 ) {
 360                         // We need stop the CACHE as RAM for this CPU too
 361                         #include "cpu/amd/car/cache_as_ram_post.c"
 362                         stop_this_cpu(); // it will stop all cores except core0 of cpu0
 363                 }
 364         }
 365
 366         init_timer(); // only do it it first CPU
 367
 368
 369         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 370         uart_init();
 371         console_init();
 372
 373         /* Halt if there was a built in self test failure */
 374         report_bist_failure(bist);
 375
 376         setup_s2895_resource_map();
 377
 378         needs_reset = setup_coherent_ht_domain();
 379
 380 #if CONFIG_LOGICAL_CPUS==1
 381         // It is said that we should start core1 after all core0 launched
 382         start_other_cores();
 383 #endif
 384
 385         needs_reset |= ht_setup_chains_x();
 386
 387         needs_reset |= ck804_early_setup_x();
 388
 389         if (needs_reset) {
 390                 print_info("ht reset -\r\n");
 391                 soft_reset();
 392         }
 393
 394         enable_smbus();
 395
 396         memreset_setup();
 397         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 398
 399 #if 1
 400         {
 401         /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
 402         unsigned v_esp;
 403         __asm__ volatile (
 404                 "movl   %%esp, %0\n\t"
 405                 : "=a" (v_esp)
 406         );
 407 #if CONFIG_USE_INIT
 408         printk_debug("v_esp=%08x\r\n", v_esp);
 409 #else
 410         print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 411 #endif
 412         }
 413
 414 #endif
 415 #if 1
 416
 417 cpu_reset_x:
 418
 419 #if CONFIG_USE_INIT
 420         printk_debug("cpu_reset = %08x\r\n",cpu_reset);
 421 #else
 422         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 423 #endif
 424
 425         if(cpu_reset == 0) {
 426                 print_debug("Clearing initial memory region: ");
 427         }
 428         print_debug("No cache as ram now - ");
 429
 430         /* store cpu_reset to ebx */
 431         __asm__ volatile (
 432                 "movl %0, %%ebx\n\t"
 433                 ::"a" (cpu_reset)
 434         );
 435
 436         if(cpu_reset==0) {
 437 #define CLEAR_FIRST_1M_RAM 1
 438 #include "cpu/amd/car/cache_as_ram_post.c"
 439         }
 440         else {
 441 #undef CLEAR_FIRST_1M_RAM
 442 #include "cpu/amd/car/cache_as_ram_post.c"
 443         }
 444
 445         __asm__ volatile (
 446                 /* set new esp */ /* before _RAMBASE */
 447                 "subl   %0, %%ebp\n\t"
 448                 "subl   %0, %%esp\n\t"
 449                 ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
 450         );
 451
 452         {
 453                 unsigned new_cpu_reset;
 454
 455                 /* get back cpu_reset from ebx */
 456                 __asm__ volatile (
 457                         "movl %%ebx, %0\n\t"
 458                         :"=a" (new_cpu_reset)
 459                 );
 460
 461                 /* We can not go back any more, we lost old stack data in cache as ram*/
 462                 if(new_cpu_reset==0) {
 463                         print_debug("Use Ram as Stack now - done\r\n");
 464                 } else
 465                 {
 466                         print_debug("Use Ram as Stack now - \r\n");
 467                 }
 468 #if CONFIG_USE_INIT
 469                 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
 470 #else
 471                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 472 #endif
 473
 474                 /*copy and execute linuxbios_ram */
 475                 copy_and_run(new_cpu_reset);
 476                 /* We will not return */
 477         }
 478 #endif
 479
 480
 481         print_err("should not be here -\r\n");
 482 }