src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5 //#define K8_SCAN_PCI_BUS 1
   6
   7 //used by raminit
   8 #define QRANK_DIMM_SUPPORT 1
   9
  10 #if CONFIG_LOGICAL_CPUS==1
  11 #define SET_NB_CFG_54 1
  12 #endif
  13
  14 #include <stdint.h>
  15 #include <string.h>
  16 #include <device/pci_def.h>
  17 #include <arch/io.h>
  18 #include <device/pnp_def.h>
  19 #include <arch/romcc_io.h>
  20 #include <cpu/x86/lapic.h>
  21 #include "option_table.h"
  22 #include "pc80/mc146818rtc_early.c"
  23
  24 #if CONFIG_USE_FAILOVER_IMAGE==0
  25 #include "pc80/serial.c"
  26 #include "arch/i386/lib/console.c"
  27 #include "ram/ramtest.c"
  28
  29 #include <cpu/amd/model_fxx_rev.h>
  30
  31 #include "northbridge/amd/amdk8/incoherent_ht.c"
  32 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  33 #include "northbridge/amd/amdk8/raminit.h"
  34 #include "cpu/amd/model_fxx/apic_timer.c"
  35 #include "lib/delay.c"
  36
  37 #endif
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  42 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  43 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  44
  45 #define SUPERIO_GPIO_IO_BASE 0x400
  46
  47 #if CONFIG_USE_FAILOVER_IMAGE==0
  48
  49 #include "cpu/x86/bist.h"
  50
  51 #include "northbridge/amd/amdk8/debug.c"
  52
  53 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  54
  55 #include "northbridge/amd/amdk8/setup_resource_map.c"
  56
  57 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  58
  59 static void memreset_setup(void)
  60 {
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 static void sio_gpio_setup(void){
  68
  69         unsigned value;
  70
  71         /*Enable onboard scsi*/
  72         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  73         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  74         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  75
  76 }
  77
  78 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  79 {
  80         /* nothing to do */
  81 }
  82
  83 static inline int spd_read_byte(unsigned device, unsigned address)
  84 {
  85         return smbus_read_byte(device, address);
  86 }
  87
  88 #include "northbridge/amd/amdk8/raminit.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "sdram/generic_sdram.c"
  91
  92  /* tyan does not want the default */
  93 #include "resourcemap.c"
  94
  95 #include "cpu/amd/dualcore/dualcore.c"
  96
  97 #define CK804_NUM 2
  98 #define CK804B_BUSN 0x80
  99 #define CK804_USE_NIC 1
 100 #define CK804_USE_ACI 1
 101
 102 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 103
 104 //set GPIO to input mode
 105 #define CK804_MB_SETUP \
 106         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 107         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 108         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 109         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 110         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 111         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 112
 113 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 114
 115 #include "cpu/amd/car/copy_and_run.c"
 116
 117 #include "cpu/amd/car/post_cache_as_ram.c"
 118
 119 #include "cpu/amd/model_fxx/init_cpus.c"
 120
 121 #endif
 122
 123 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 124
 125 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 126 #include "northbridge/amd/amdk8/early_ht.c"
 127
 128 static void sio_setup(void)
 129 {
 130
 131         unsigned value;
 132         uint32_t dword;
 133         uint8_t byte;
 134
 135         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 136
 137         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 138         byte |= 0x20;
 139         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 140
 141         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 142         dword |= (1<<29)|(1<<0);
 143         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 144
 145         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 146         dword |= (1<<16);
 147         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 148
 149         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 150         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 151         value &= 0xbf;
 152         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 153
 154 }
 155
 156 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 157 {
 158         unsigned last_boot_normal_x = last_boot_normal();
 159
 160         /* Is this a cpu only reset? or Is this a secondary cpu? */
 161         if ((cpu_init_detectedx) || (!boot_cpu())) {
 162         if (last_boot_normal_x) {
 163         goto normal_image;
 164         } else {
 165         goto fallback_image;
 166         }
 167         }
 168
 169         /* Nothing special needs to be done to find bus 0 */
 170         /* Allow the HT devices to be found */
 171
 172         enumerate_ht_chain();
 173
 174         sio_setup();
 175
 176         /* Setup the ck804 */
 177         ck804_enable_rom();
 178
 179         /* Is this a deliberate reset by the bios */
 180 //      post_code(0x22);
 181         if (bios_reset_detected() && last_boot_normal_x) {
 182         goto normal_image;
 183         }
 184         /* This is the primary cpu how should I boot? */
 185         else if (do_normal_boot()) {
 186         goto normal_image;
 187         }
 188         else {
 189         goto fallback_image;
 190         }
 191  normal_image:
 192 //      post_code(0x23);
 193         __asm__ volatile ("jmp __normal_image"
 194         : /* outputs */
 195         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 196         );
 197
 198  fallback_image:
 199 //      post_code(0x25);
 200 #if CONFIG_HAVE_FAILOVER_BOOT==1
 201         __asm__ volatile ("jmp __fallback_image"
 202         : /* outputs */
 203         : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 204         )
 205 #endif
 206         ;
 207 }
 208 #endif
 209
 210 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 211
 212 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 213 {
 214 #if CONFIG_HAVE_FAILOVER_BOOT==1
 215         #if CONFIG_USE_FAILOVER_IMAGE==1
 216         failover_process(bist, cpu_init_detectedx);
 217         #else
 218         real_main(bist, cpu_init_detectedx);
 219         #endif
 220 #else
 221         #if CONFIG_USE_FALLBACK_IMAGE == 1
 222         failover_process(bist, cpu_init_detectedx);
 223         #endif
 224         real_main(bist, cpu_init_detectedx);
 225 #endif
 226 }
 227
 228 #if CONFIG_USE_FAILOVER_IMAGE==0
 229
 230 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 231 {
 232         static const uint16_t spd_addr [] = {
 233                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 234                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 235 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 236                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 237                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 238 #endif
 239         };
 240
 241         int needs_reset;
 242         unsigned bsp_apicid = 0;
 243
 244         struct mem_controller ctrl[8];
 245         unsigned nodes;
 246
 247         if (bist == 0) {
 248                 bsp_apicid = init_cpus(cpu_init_detectedx);
 249         }
 250
 251 //      post_code(0x32);
 252
 253         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 254         uart_init();
 255         console_init();
 256
 257         /* Halt if there was a built in self test failure */
 258         report_bist_failure(bist);
 259
 260         sio_gpio_setup();
 261
 262         setup_mb_resource_map();
 263 #if 0
 264         dump_pci_device(PCI_DEV(0, 0x18, 0));
 265         dump_pci_device(PCI_DEV(0, 0x19, 0));
 266 #endif
 267
 268         needs_reset = setup_coherent_ht_domain();
 269
 270         wait_all_core0_started();
 271 #if CONFIG_LOGICAL_CPUS==1
 272         // It is said that we should start core1 after all core0 launched
 273         start_other_cores();
 274         wait_all_other_cores_started(bsp_apicid);
 275 #endif
 276
 277         needs_reset |= ht_setup_chains_x();
 278
 279         needs_reset |= ck804_early_setup_x();
 280
 281         if (needs_reset) {
 282                 print_info("ht reset -\r\n");
 283         //      soft_reset();
 284         }
 285
 286         allow_all_aps_stop(bsp_apicid);
 287
 288         nodes = get_nodes();
 289         //It's the time to set ctrl now;
 290         fill_mem_ctrl(nodes, ctrl, spd_addr);
 291
 292         enable_smbus();
 293 #if 0
 294         dump_spd_registers(&cpu[0]);
 295 #endif
 296 #if 0
 297         dump_smbus_registers();
 298 #endif
 299
 300         memreset_setup();
 301         sdram_initialize(nodes, ctrl);
 302
 303 #if 0
 304         print_pci_devices();
 305 #endif
 306
 307 #if 0
 308         dump_pci_devices();
 309 #endif
 310
 311         post_cache_as_ram();
 312 }
 313 #endif