src/mainboard/tyan/s2895/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FAILOVER_IMAGE
   6         default ROM_SECTION_SIZE   = FAILOVER_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
   8 else
   9     if USE_FALLBACK_IMAGE
  10         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  11         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  12     else
  13         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  14         default ROM_SECTION_OFFSET = 0
  15     end
  16 end
  17
  18 ##
  19 ## Compute the start location and size size of
  20 ## The coreboot bootloader.
  21 ##
  22 default PAYLOAD_SIZE         = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  24
  25 ##
  26 ## Compute where this copy of coreboot will start in the boot rom
  27 ##
  28 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  29
  30 ##
  31 ## Compute a range of ROM that can cached to speed up coreboot,
  32 ## execution speed.
  33 ##
  34 ## XIP_ROM_SIZE must be a power of 2.
  35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  36 ##
  37 default XIP_ROM_SIZE=65536
  38
  39 if USE_FAILOVER_IMAGE
  40         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  41 else
  42         if USE_FALLBACK_IMAGE
  43                 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  44         else
  45                 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  46         end
  47 end
  48
  49 arch i386 end
  50
  51 ##
  52 ## Build the objects we have code for in this directory.
  53 ##
  54
  55 driver mainboard.o
  56 #needed by irq_tables and mptable and acpi_tables
  57 object get_bus_conf.o
  58
  59 if HAVE_MP_TABLE object mptable.o end
  60 if HAVE_PIRQ_TABLE object irq_tables.o end
  61 #object reset.o
  62
  63 if HAVE_ACPI_TABLES
  64         object acpi_tables.o
  65         makerule dsdt.c
  66                 depends "$(MAINBOARD)/dsdt.dsl"
  67                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
  68                 action  "mv dsdt.hex dsdt.c"
  69         end
  70         object ./dsdt.o
  71         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  72         #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
  73 end
  74
  75 if USE_DCACHE_RAM
  76
  77 if CONFIG_USE_INIT
  78         makerule ./auto.o
  79                 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  80                 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  81         end
  82 else
  83         makerule ./auto.inc
  84                 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  85                 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
  86                 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  87                 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  88         end
  89 end
  90
  91 else
  92         ##
  93         ## Romcc output
  94         ##
  95         makerule ./failover.E
  96                 depends "$(MAINBOARD)/failover.c ../romcc"
  97                 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  98         end
  99
 100         makerule ./failover.inc
 101                 depends "$(MAINBOARD)/failover.c ../romcc"
 102                 action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 103         end
 104
 105         makerule ./auto.E
 106                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
 107                 action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 108         end
 109
 110         makerule ./auto.inc
 111                 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
 112                 action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 113         end
 114
 115 end
 116
 117 ##
 118 ## Build our 16 bit and 32 bit coreboot entry code
 119 ##
 120 if HAVE_FAILOVER_BOOT
 121         if USE_FAILOVER_IMAGE
 122                 mainboardinit cpu/x86/16bit/entry16.inc
 123                 ldscript /cpu/x86/16bit/entry16.lds
 124         end
 125 else
 126         if USE_FALLBACK_IMAGE
 127                 mainboardinit cpu/x86/16bit/entry16.inc
 128                 ldscript /cpu/x86/16bit/entry16.lds
 129         end
 130 end
 131
 132 mainboardinit cpu/x86/32bit/entry32.inc
 133
 134 if USE_DCACHE_RAM
 135         if CONFIG_USE_INIT
 136                 ldscript /cpu/x86/32bit/entry32.lds
 137         end
 138
 139         if CONFIG_USE_INIT
 140                 ldscript /cpu/amd/car/cache_as_ram.lds
 141         end
 142 end
 143
 144 ##
 145 ## Build our reset vector (This is where coreboot is entered)
 146 ##
 147 if HAVE_FAILOVER_BOOT
 148     if USE_FAILOVER_IMAGE
 149         mainboardinit cpu/x86/16bit/reset16.inc
 150         ldscript /cpu/x86/16bit/reset16.lds
 151     else
 152         mainboardinit cpu/x86/32bit/reset32.inc
 153         ldscript /cpu/x86/32bit/reset32.lds
 154     end
 155 else
 156     if USE_FALLBACK_IMAGE
 157         mainboardinit cpu/x86/16bit/reset16.inc
 158         ldscript /cpu/x86/16bit/reset16.lds
 159     else
 160         mainboardinit cpu/x86/32bit/reset32.inc
 161         ldscript /cpu/x86/32bit/reset32.lds
 162     end
 163 end
 164
 165 if USE_DCACHE_RAM
 166 else
 167         ### Should this be in the northbridge code?
 168         mainboardinit arch/i386/lib/cpu_reset.inc
 169 end
 170
 171 ##
 172 ## Include an id string (For safe flashing)
 173 ##
 174 mainboardinit southbridge/nvidia/ck804/id.inc
 175 ldscript /southbridge/nvidia/ck804/id.lds
 176
 177 ##
 178 ## ROMSTRAP table for CK804
 179 ##
 180 if HAVE_FAILOVER_BOOT
 181         if USE_FAILOVER_IMAGE
 182                 mainboardinit southbridge/nvidia/ck804/romstrap.inc
 183                 ldscript /southbridge/nvidia/ck804/romstrap.lds
 184         end
 185 else
 186         if USE_FALLBACK_IMAGE
 187                 mainboardinit southbridge/nvidia/ck804/romstrap.inc
 188                 ldscript /southbridge/nvidia/ck804/romstrap.lds
 189         end
 190 end
 191
 192 if USE_DCACHE_RAM
 193         ##
 194         ## Setup Cache-As-Ram
 195         ##
 196         mainboardinit cpu/amd/car/cache_as_ram.inc
 197 end
 198
 199 ###
 200 ### This is the early phase of coreboot startup
 201 ### Things are delicate and we test to see if we should
 202 ### failover to another image.
 203 ###
 204 if HAVE_FAILOVER_BOOT
 205         if USE_FAILOVER_IMAGE
 206                 if USE_DCACHE_RAM
 207                         ldscript /arch/i386/lib/failover_failover.lds
 208                 end
 209         end
 210 else
 211         if USE_FALLBACK_IMAGE
 212                 if USE_DCACHE_RAM
 213                         ldscript /arch/i386/lib/failover.lds
 214                 else
 215                         mainboardinit ./failover.inc
 216                 end
 217         end
 218 end
 219
 220 ##
 221 ## Setup RAM
 222 ##
 223 if USE_DCACHE_RAM
 224
 225         if CONFIG_USE_INIT
 226                 initobject auto.o
 227         else
 228                 mainboardinit ./auto.inc
 229         end
 230
 231 else
 232         # ROMCC
 233         mainboardinit cpu/x86/fpu/enable_fpu.inc
 234         mainboardinit cpu/x86/mmx/enable_mmx.inc
 235         mainboardinit cpu/x86/sse/enable_sse.inc
 236         mainboardinit ./auto.inc
 237         mainboardinit cpu/x86/sse/disable_sse.inc
 238         mainboardinit cpu/x86/mmx/disable_mmx.inc
 239
 240 end
 241
 242 ##
 243 ## Include the secondary Configuration files
 244 ##
 245 config chip.h
 246
 247 # sample config for tyan/s2895
 248 chip northbridge/amd/amdk8/root_complex
 249         device apic_cluster 0 on
 250                 chip cpu/amd/socket_940
 251                         device apic 0 on end
 252                 end
 253         end
 254         device pci_domain 0 on
 255                 chip northbridge/amd/amdk8 #mc0
 256                         device pci 18.0 on #  northbridge
 257                                 #  devices on link 0, link 0 == LDT 0
 258                                 chip southbridge/nvidia/ck804
 259                                         device pci 0.0 on end   # HT
 260                                         device pci 1.0 on # LPC
 261                                                 chip superio/smsc/lpc47b397
 262                                                         device pnp 2e.0 on #  Floppy
 263                                                                 io 0x60 = 0x3f0
 264                                                                 irq 0x70 = 6
 265                                                                 drq 0x74 = 2
 266                                                         end
 267                                                         device pnp 2e.3 on #  Parallel Port
 268                                                                 io 0x60 = 0x378
 269                                                                 irq 0x70 = 7
 270                                                                 drq 0x74 = 4
 271                                                         end
 272                                                         device pnp 2e.4 on #  Com1
 273                                                                 io 0x60 = 0x3f8
 274                                                                 irq 0x70 = 4
 275                                                         end
 276                                                         device pnp 2e.5 off #  Com2
 277                                                                 io 0x60 = 0x2f8
 278                                                                 irq 0x70 = 3
 279                                                         end
 280                                                         device pnp 2e.7 on #  Keyboard
 281                                                                 io 0x60 = 0x60
 282                                                                 io 0x62 = 0x64
 283                                                                 irq 0x70 = 1
 284                                                                 irq 0x72 = 12
 285                                                         end
 286                                                         device pnp 2e.8 on # HW Monitor
 287                                                                 io 0x60 = 0x480
 288                                                                 chip drivers/generic/generic # LM95221 CPU temp
 289                                                                         device i2c 2b on end
 290                                                                 end
 291                                                                 chip drivers/generic/generic # EMCT03
 292                                                                         device i2c 54 on end
 293                                                                 end
 294                                                         end
 295                                                         device  pnp 2e.a on #  RT
 296                                                                 io 0x60 = 0x400
 297                                                         end
 298                                                 end
 299                                         end
 300                                         device pci 1.1 on # SM 0
 301                                                 chip drivers/generic/generic #dimm 0-0-0
 302                                                         device i2c 50 on end
 303                                                 end
 304                                                 chip drivers/generic/generic #dimm 0-0-1
 305                                                         device i2c 51 on end
 306                                                 end
 307                                                 chip drivers/generic/generic #dimm 0-1-0
 308                                                         device i2c 52 on end
 309                                                 end
 310                                                 chip drivers/generic/generic #dimm 0-1-1
 311                                                         device i2c 53 on end
 312                                                 end
 313                                                 chip drivers/generic/generic #dimm 1-0-0
 314                                                         device i2c 54 on end
 315                                                 end
 316                                                 chip drivers/generic/generic #dimm 1-0-1
 317                                                         device i2c 55 on end
 318                                                 end
 319                                                 chip drivers/generic/generic #dimm 1-1-0
 320                                                         device i2c 56 on end
 321                                                 end
 322                                                 chip drivers/generic/generic #dimm 1-1-1
 323                                                         device i2c 57 on end
 324                                                 end
 325                                         end # SM
 326                                         device pci 1.1 on # SM 1
 327                                                 chip drivers/generic/generic #MAC EEPROM
 328                                                         device i2c 51 on end
 329                                                 end
 330
 331                                         end # SM
 332                                         device pci 2.0 on end # USB 1.1
 333                                         device pci 2.1 on end # USB 2
 334                                         device pci 4.0 on end # ACI
 335                                         device pci 4.1 off end # MCI
 336                                         device pci 6.0 on end # IDE
 337                                         device pci 7.0 on end # SATA 1
 338                                         device pci 8.0 on end # SATA 0
 339                                         device pci 9.0 on end # PCI
 340                                         device pci a.0 on end # NIC
 341                                         device pci b.0 off end # PCI E 3
 342                                         device pci c.0 off end # PCI E 2
 343                                         device pci d.0 off end # PCI E 1
 344                                         device pci e.0 on end # PCI E 0
 345                                         register "ide0_enable" = "1"
 346                                         register "ide1_enable" = "1"
 347                                         register "sata0_enable" = "1"
 348                                         register "sata1_enable" = "1"
 349 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 350 #                                       register "raid_rom_address" = "0xfff90000"
 351                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 352                                         register "mac_eeprom_addr" = "0x51"
 353                                 end
 354                         end #  device pci 18.0
 355                         device pci 18.0 on end # Link 1
 356                         device pci 18.0 on
 357                         #  devices on link 2, link 2 == LDT 2
 358                                 chip southbridge/amd/amd8131
 359                                         # the on/off keyword is mandatory
 360                                         device pci 0.0 on end
 361                                         device pci 0.1 on end
 362                                         device pci 1.0 on
 363                                                 chip drivers/pci/onboard
 364                                                         device pci 6.0 on end # lsi scsi
 365                                                         device pci 6.1 on end
 366                                                 end
 367                                         end
 368                                         device pci 1.1 on end
 369                                 end
 370                         end # device pci 18.0
 371                         device pci 18.1 on end
 372                         device pci 18.2 on end
 373                         device pci 18.3 on end
 374                 end #mc0
 375
 376                 chip northbridge/amd/amdk8
 377                         device pci 19.0 on #  northbridge
 378                                 #  devices on link 0, link 0 == LDT 0
 379                                 chip southbridge/nvidia/ck804
 380                                         device pci 0.0 on end   # HT
 381                                         device pci 1.0 on end   # LPC
 382                                         device pci 1.1 off end # SM
 383                                         device pci 2.0 off end # USB 1.1
 384                                         device pci 2.1 off end # USB 2
 385                                         device pci 4.0 off end # ACI
 386                                         device pci 4.1 off end # MCI
 387                                         device pci 6.0 off end # IDE
 388                                         device pci 7.0 off end # SATA 1
 389                                         device pci 8.0 off end # SATA 0
 390                                         device pci 9.0 off end # PCI
 391                                         device pci a.0 on end # NIC
 392                                         device pci b.0 off end # PCI E 3
 393                                         device pci c.0 off end # PCI E 2
 394                                         device pci d.0 off end # PCI E 1
 395                                         device pci e.0 on end # PCI E 0
 396 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 397                                         register "mac_eeprom_smbus" = "3"
 398                                         register "mac_eeprom_addr" = "0x51"
 399                                 end
 400                         end #  device pci 19.0
 401
 402                         device pci 19.0 on end
 403                         device pci 19.0 on end
 404                         device pci 19.1 on end
 405                         device pci 19.2 on end
 406                         device pci 19.3 on end
 407                 end
 408         end # PCI domain
 409
 410 #       chip drivers/generic/debug
 411 #               device pnp 0.0 off end # chip name
 412 #               device pnp 0.1 off end # pci_regs_all
 413 #               device pnp 0.2 off end # mem
 414 #               device pnp 0.3 off end # cpuid
 415 #               device pnp 0.4 on  end # smbus_regs_all
 416 #               device pnp 0.5 off end # dual core msr
 417 #               device pnp 0.6 off end # cache size
 418 #               device pnp 0.7 off end # tsc
 419 #       end
 420 end # root_complex