src/mainboard/tyan/s2892/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15
  16 #include <console/console.h>
  17 #include "lib/ramtest.c"
  18
  19 #include <cpu/amd/model_fxx_rev.h>
  20
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  23 #include "northbridge/amd/amdk8/raminit.h"
  24 #include "cpu/amd/model_fxx/apic_timer.c"
  25 #include "lib/delay.c"
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/x86/mtrr/earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 static void memreset(int controllers, const struct mem_controller *ctrl)
  40 {
  41 }
  42
  43 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  44 {
  45         /* nothing to do */
  46 }
  47
  48 static inline int spd_read_byte(unsigned device, unsigned address)
  49 {
  50         return smbus_read_byte(device, address);
  51 }
  52
  53 #include "northbridge/amd/amdk8/raminit.c"
  54 #include "northbridge/amd/amdk8/coherent_ht.c"
  55 #include "lib/generic_sdram.c"
  56
  57  /* tyan does not want the default */
  58 #include "resourcemap.c"
  59
  60 #include "cpu/amd/dualcore/dualcore.c"
  61
  62 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  63 //set GPIO to input mode
  64 #define CK804_MB_SETUP \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  68         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  69
  70 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  71
  72
  73
  74 #include "cpu/amd/car/post_cache_as_ram.c"
  75
  76 #include "cpu/amd/model_fxx/init_cpus.c"
  77
  78 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  79 #include "northbridge/amd/amdk8/early_ht.c"
  80
  81 static void sio_setup(void)
  82 {
  83         uint32_t dword;
  84         uint8_t byte;
  85
  86         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  87         byte |= 0x20;
  88         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  89
  90         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  91         dword |= (1<<0);
  92         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  93 }
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const uint16_t spd_addr [] = {
  98                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  99                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 100 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 101                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 102                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 103 #endif
 104         };
 105
 106         int needs_reset;
 107         unsigned bsp_apicid = 0;
 108
 109         struct mem_controller ctrl[8];
 110         unsigned nodes;
 111
 112         if (!cpu_init_detectedx && boot_cpu()) {
 113                 /* Nothing special needs to be done to find bus 0 */
 114                 /* Allow the HT devices to be found */
 115
 116                 enumerate_ht_chain();
 117
 118                 sio_setup();
 119
 120                 /* Setup the ck804 */
 121                 ck804_enable_rom();
 122         }
 123
 124         if (bist == 0) {
 125                 bsp_apicid = init_cpus(cpu_init_detectedx);
 126         }
 127
 128 //      post_code(0x32);
 129
 130         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 131         uart_init();
 132         console_init();
 133
 134         /* Halt if there was a built in self test failure */
 135         report_bist_failure(bist);
 136
 137         setup_mb_resource_map();
 138
 139         needs_reset = setup_coherent_ht_domain();
 140
 141         wait_all_core0_started();
 142 #if CONFIG_LOGICAL_CPUS==1
 143         // It is said that we should start core1 after all core0 launched
 144         start_other_cores();
 145         wait_all_other_cores_started(bsp_apicid);
 146 #endif
 147
 148         needs_reset |= ht_setup_chains_x();
 149
 150         needs_reset |= ck804_early_setup_x();
 151
 152         if (needs_reset) {
 153                 printk(BIOS_INFO, "ht reset -\n");
 154                 soft_reset();
 155         }
 156
 157         allow_all_aps_stop(bsp_apicid);
 158
 159         nodes = get_nodes();
 160         //It's the time to set ctrl now;
 161         fill_mem_ctrl(nodes, ctrl, spd_addr);
 162
 163         enable_smbus();
 164
 165         sdram_initialize(nodes, ctrl);
 166
 167         post_cache_as_ram();
 168 }
 169