2 * This file is part of the coreboot project.
4 * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
5 * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
7 * ISA portions taken from QEMU acpi-dsdt.dsl.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License v2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
25 Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
27 /* For now only define 2 power states:
28 * - S0 which is fully on
29 * - S5 which is soft off
30 * Any others would involve declaring the wake up methods.
32 Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
33 Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
35 /* Root of the bus hierarchy */
38 /* Top PCI device (CK804) */
41 Name (_HID, EisaId ("PNP0A03"))
55 Method (_CRS, 0, NotSerialized)
57 Name (BUF0, ResourceTemplate ()
60 0x0CF8, // Address Range Minimum
61 0x0CF8, // Address Range Maximum
62 0x01, // Address Alignment
63 0x08, // Address Length
65 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
66 0x0000, // Address Space Granularity
67 0x0000, // Address Range Minimum
68 0x0CF7, // Address Range Maximum
69 0x0000, // Address Translation Offset
70 0x0CF8, // Address Length
73 /* Methods bellow use SSDT to get actual MMIO regs
74 The IO ports are from 0xd00, optionally an VGA,
75 otherwise the info from MMIO is used.
78 Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
79 Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
80 Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
84 /* PCI Routing Table */
85 Name (_PRT, Package () {
86 /* Since source is 0, index is IRQ. */
87 /* in ABCD, A=0, B=1, C=2, D=3 */
88 /* SlotFFFF, ABCD, source, index */
89 Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x0A }, /* 0x1 SMBUS IRQ 10 */
90 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, /* 0x2 USB IRQ 21 */
91 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x14 }, /* 0x2 USB IRQ 20 */
92 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, /* 0x7 SATA 0 IRQ 23 */
93 Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x16 }, /* 0x8 SATA 1 IRQ 22 */
98 Name (_ADR, 0x00090000)
101 Name (_PRT, Package () {
102 Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, /* 1:04 PCI 32 IRQ16-IRQ19 */
103 Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
104 Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
105 Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
106 Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 }, /* 1:06 Onboard ATI Rage IRQ 18 */
107 Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, /* 1:08 Onboard Intel NIC IRQ 18 */
111 /* 2:00 PCIe x16 SB IRQ 18 */
114 Name (_ADR, 0x000e0000)
117 Name (_PRT, Package () {
118 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 }, /* PCIE IRQ16-IRQ19 */
119 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
120 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
121 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
125 /* 2:00 PCIe x4 SB IRQ 17 */
128 Name (_ADR, 0x000e0000)
131 Name (_PRT, Package () {
132 Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 }, /* PCIE IRQ16-IRQ19 */
133 Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
134 Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
135 Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
140 Name (_HID, EisaId ("PNP0A05"))
141 Name (_ADR, 0x00010000)
143 /* PS/2 keyboard (seems to be important for WinXP install) */
146 Name (_HID, EisaId ("PNP0303"))
147 Method (_STA, 0, NotSerialized)
151 Method (_CRS, 0, NotSerialized)
153 Name (TMP, ResourceTemplate () {
154 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
155 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
165 Name (_HID, EisaId ("PNP0F13"))
166 Method (_STA, 0, NotSerialized)
170 Method (_CRS, 0, NotSerialized)
172 Name (TMP, ResourceTemplate () {
182 Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
183 Method (_STA, 0, NotSerialized)
187 Method (_CRS, 0, NotSerialized)
189 Name (TMP, ResourceTemplate () {
190 FixedIO (0x0378, 0x10)
197 /* Floppy controller */
200 Name (_HID, EisaId ("PNP0700"))
201 Method (_STA, 0, NotSerialized)
205 Method (_CRS, 0, NotSerialized)
207 Name (BUF0, ResourceTemplate () {
208 FixedIO (0x03F0, 0x08)
210 DMA (Compatibility, NotBusMaster, Transfer8) {2}
218 /* AMD 8131 PCI-X tunnel */
221 Name (_HID, EisaId ("PNP0A03"))
226 /* There is no _PRT Here because I don't know what to
227 * put in it. Since the 8131 has its own APIC, it
228 * isn't wired to other IRQs. */
230 Method (_CRS, 0, NotSerialized)
232 Name (BUF0, ResourceTemplate ()
235 0x0CF8, // Address Range Minimum
236 0x0CF8, // Address Range Maximum
237 0x01, // Address Alignment
238 0x08, // Address Length
241 /* Methods bellow use SSDT to get actual MMIO regs
242 The IO ports are from 0xd00, optionally an VGA,
243 otherwise the info from MMIO is used.
244 \_SB.GXXX(node, link)
246 Concatenate (\_SB.GMEM (0x00, 0x02), BUF0, Local1)
247 Concatenate (\_SB.GIOR (0x00, 0x02), Local1, Local2)
248 Concatenate (\_SB.GWBN (0x00, 0x02), Local2, Local3)
252 /* Channel A PCIX 133 */
255 Name (_ADR, 0x00000000)
258 Name (_PRT, Package () {
259 Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1b }, /* PCIE IRQ24-IRQ27 shifted 3*/
260 Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
261 Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
262 Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1a },
263 Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1a }, /* PCIE IRQ24-IRQ27 shifted 2*/
264 Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1b },
265 Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
266 Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
270 /* Channel B PCIX 100 */
271 Device (PCXS) /* Onboard NIC, SO-DIMM, Slot 4 */
273 Name (_ADR, 0x00010000)
276 Name (_PRT, Package () {
277 Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
278 Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x1d },
279 Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x1e },
280 Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x1f },
281 Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x1c }, /* PCIE IRQ28-IRQ31 */
282 Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x1d },
283 Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x1e },
284 Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x1f },
285 Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1d }, /* PCIE IRQ28-IRQ31 shifted 2 */
286 Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1e },
287 Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1f },
288 Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1c },