src/mainboard/tyan/s2892/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #if CONFIG_USE_INIT == 0
  25 #include "lib/memcpy.c"
  26 #endif
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  32
  33 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  34 #include "cpu/x86/bist.h"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 static void memreset_setup(void)
  41 {
  42 }
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl)
  45 {
  46 }
  47
  48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50         /* nothing to do */
  51 }
  52
  53 static inline int spd_read_byte(unsigned device, unsigned address)
  54 {
  55         return smbus_read_byte(device, address);
  56 }
  57
  58 #define QRANK_DIMM_SUPPORT 1
  59
  60 #include "northbridge/amd/amdk8/raminit.c"
  61 #include "northbridge/amd/amdk8/coherent_ht.c"
  62 #include "sdram/generic_sdram.c"
  63
  64  /* tyan does not want the default */
  65 #include "resourcemap.c"
  66
  67 #if CONFIG_LOGICAL_CPUS==1
  68 #define SET_NB_CFG_54 1
  69 #endif
  70 #include "cpu/amd/dualcore/dualcore.c"
  71
  72 #define CK804_NUM 1
  73 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  74 //set GPIO to input mode
  75 #define CK804_MB_SETUP \
  76                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  77                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  78                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  79                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  80
  81 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  82
  83 #include "cpu/amd/car/copy_and_run.c"
  84
  85 #include "cpu/amd/car/post_cache_as_ram.c"
  86
  87 #include "cpu/amd/model_fxx/init_cpus.c"
  88
  89 #if USE_FALLBACK_IMAGE == 1
  90
  91 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 static void sio_setup(void)
  95 {
  96
  97         unsigned value;
  98         uint32_t dword;
  99         uint8_t byte;
 100
 101         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 102         byte |= 0x20;
 103         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 104
 105         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 106         dword |= (1<<0);
 107         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 108
 109 }
 110
 111 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 112 {
 113         unsigned last_boot_normal_x = last_boot_normal();
 114
 115         /* Is this a cpu only reset? or Is this a secondary cpu? */
 116         if ((cpu_init_detectedx) || (!boot_cpu())) {
 117         if (last_boot_normal_x) {
 118         goto normal_image;
 119         } else {
 120         goto fallback_image;
 121         }
 122         }
 123
 124         /* Nothing special needs to be done to find bus 0 */
 125         /* Allow the HT devices to be found */
 126
 127         enumerate_ht_chain();
 128
 129         sio_setup();
 130
 131         /* Setup the ck804 */
 132         ck804_enable_rom();
 133
 134         /* Is this a deliberate reset by the bios */
 135 //      post_code(0x22);
 136         if (bios_reset_detected() && last_boot_normal_x) {
 137         goto normal_image;
 138         }
 139         /* This is the primary cpu how should I boot? */
 140         else if (do_normal_boot()) {
 141         goto normal_image;
 142         }
 143         else {
 144         goto fallback_image;
 145         }
 146  normal_image:
 147 //      post_code(0x23);
 148         __asm__ volatile ("jmp __normal_image"
 149         : /* outputs */
 150         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 151         );
 152
 153  fallback_image:
 154 //      post_code(0x25);
 155         ;
 156 }
 157 #endif
 158
 159 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 160
 161 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 162 {
 163
 164 #if USE_FALLBACK_IMAGE == 1
 165                 failover_process(bist, cpu_init_detectedx);
 166 #endif
 167         real_main(bist, cpu_init_detectedx);
 168
 169 }
 170
 171 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 172 {
 173         static const uint16_t spd_addr [] = {
 174                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 175                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 176 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 177                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 178                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 179 #endif
 180         };
 181
 182         int needs_reset;
 183         unsigned bsp_apicid = 0;
 184
 185         struct mem_controller ctrl[8];
 186         unsigned nodes;
 187
 188         if (bist == 0) {
 189                 init_cpus(cpu_init_detectedx);
 190         }
 191
 192 //      post_code(0x32);
 193
 194         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 195         uart_init();
 196         console_init();
 197
 198         /* Halt if there was a built in self test failure */
 199         report_bist_failure(bist);
 200
 201         setup_s2892_resource_map();
 202 #if 0
 203         dump_pci_device(PCI_DEV(0, 0x18, 0));
 204         dump_pci_device(PCI_DEV(0, 0x19, 0));
 205 #endif
 206
 207         needs_reset = setup_coherent_ht_domain();
 208
 209         wait_all_core0_started();
 210 #if CONFIG_LOGICAL_CPUS==1
 211         // It is said that we should start core1 after all core0 launched
 212         start_other_cores();
 213         wait_all_other_cores_started(bsp_apicid);
 214 #endif
 215
 216         needs_reset |= ht_setup_chains_x();
 217
 218         needs_reset |= ck804_early_setup_x();
 219
 220         if (needs_reset) {
 221                 print_info("ht reset -\r\n");
 222                 soft_reset();
 223         }
 224
 225         allow_all_aps_stop(bsp_apicid);
 226
 227         nodes = get_nodes();
 228         //It's the time to set ctrl now;
 229         fill_mem_ctrl(nodes, ctrl, spd_addr);
 230
 231         enable_smbus();
 232 #if 0
 233         dump_spd_registers(&cpu[0]);
 234 #endif
 235 #if 0
 236         dump_smbus_registers();
 237 #endif
 238
 239         memreset_setup();
 240         sdram_initialize(nodes, ctrl);
 241
 242 #if 0
 243         print_pci_devices();
 244 #endif
 245
 246 #if 0
 247         dump_pci_devices();
 248 #endif
 249
 250         post_cache_as_ram();
 251 }