src/mainboard/tyan/s2892/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19
  20 #define post_code(x) outb(x, 0x80)
  21 #include "pc80/serial.c"
  22 #include "arch/i386/lib/console.c"
  23 #include "lib/ramtest.c"
  24
  25 #include <cpu/amd/model_fxx_rev.h>
  26
  27 #include "northbridge/amd/amdk8/incoherent_ht.c"
  28 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  29 #include "northbridge/amd/amdk8/raminit.h"
  30 #include "cpu/amd/model_fxx/apic_timer.c"
  31 #include "lib/delay.c"
  32
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "northbridge/amd/amdk8/debug.c"
  36 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  37
  38 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40
  41 #include "northbridge/amd/amdk8/setup_resource_map.c"
  42
  43 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47 }
  48
  49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51         /* nothing to do */
  52 }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/raminit.c"
  60 #include "northbridge/amd/amdk8/coherent_ht.c"
  61 #include "lib/generic_sdram.c"
  62
  63  /* tyan does not want the default */
  64 #include "resourcemap.c"
  65
  66 #include "cpu/amd/dualcore/dualcore.c"
  67
  68 #define CK804_NUM 1
  69 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  70 //set GPIO to input mode
  71 #define CK804_MB_SETUP \
  72         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  73         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  76
  77 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  78
  79 #include "cpu/amd/car/copy_and_run.c"
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #if CONFIG_USE_FALLBACK_IMAGE == 1
  86
  87 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 static void sio_setup(void)
  91 {
  92         uint32_t dword;
  93         uint8_t byte;
  94
  95         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  96         byte |= 0x20;
  97         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  98
  99         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 100         dword |= (1<<0);
 101         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 102 }
 103
 104 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         unsigned last_boot_normal_x = last_boot_normal();
 107
 108         /* Is this a cpu only reset? or Is this a secondary cpu? */
 109         if ((cpu_init_detectedx) || (!boot_cpu())) {
 110                 if (last_boot_normal_x) {
 111                         goto normal_image;
 112                 } else {
 113                         goto fallback_image;
 114                 }
 115         }
 116
 117         /* Nothing special needs to be done to find bus 0 */
 118         /* Allow the HT devices to be found */
 119
 120         enumerate_ht_chain();
 121
 122         sio_setup();
 123
 124         /* Setup the ck804 */
 125         ck804_enable_rom();
 126
 127         /* Is this a deliberate reset by the bios */
 128 //      post_code(0x22);
 129         if (bios_reset_detected() && last_boot_normal_x) {
 130                 goto normal_image;
 131         }
 132         /* This is the primary cpu how should I boot? */
 133         else if (do_normal_boot()) {
 134                 goto normal_image;
 135         }
 136         else {
 137                 goto fallback_image;
 138         }
 139  normal_image:
 140 //      post_code(0x23);
 141         __asm__ volatile ("jmp __normal_image"
 142         : /* outputs */
 143         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 144         );
 145
 146  fallback_image:
 147 //      post_code(0x25);
 148         ;
 149 }
 150 #endif
 151
 152 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 153
 154 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 155 {
 156         #if CONFIG_USE_FALLBACK_IMAGE == 1
 157         failover_process(bist, cpu_init_detectedx);
 158         #endif
 159         real_main(bist, cpu_init_detectedx);
 160 }
 161
 162 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 163 {
 164         static const uint16_t spd_addr [] = {
 165                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 166                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 167 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 168                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 169                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 170 #endif
 171         };
 172
 173         int needs_reset;
 174         unsigned bsp_apicid = 0;
 175
 176         struct mem_controller ctrl[8];
 177         unsigned nodes;
 178
 179         if (bist == 0) {
 180                 bsp_apicid = init_cpus(cpu_init_detectedx);
 181         }
 182
 183 //      post_code(0x32);
 184
 185         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 186         uart_init();
 187         console_init();
 188
 189         /* Halt if there was a built in self test failure */
 190         report_bist_failure(bist);
 191
 192         setup_mb_resource_map();
 193
 194         needs_reset = setup_coherent_ht_domain();
 195
 196         wait_all_core0_started();
 197 #if CONFIG_LOGICAL_CPUS==1
 198         // It is said that we should start core1 after all core0 launched
 199         start_other_cores();
 200         wait_all_other_cores_started(bsp_apicid);
 201 #endif
 202
 203         needs_reset |= ht_setup_chains_x();
 204
 205         needs_reset |= ck804_early_setup_x();
 206
 207         if (needs_reset) {
 208                 printk_info("ht reset -\n");
 209                 soft_reset();
 210         }
 211
 212         allow_all_aps_stop(bsp_apicid);
 213
 214         nodes = get_nodes();
 215         //It's the time to set ctrl now;
 216         fill_mem_ctrl(nodes, ctrl, spd_addr);
 217
 218         enable_smbus();
 219
 220         sdram_initialize(nodes, ctrl);
 221
 222         post_cache_as_ram();
 223 }