src/mainboard/tyan/s2891/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14
  15 #include "northbridge/amd/amdk8/cpu_rev.c"
  16 #define K8_HT_FREQ_1G_SUPPORT 0
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29 #include "cpu/amd/dualcore/dualcore.c"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void hard_reset(void)
  36 {
  37         set_bios_reset();
  38
  39         /* full reset */
  40         outb(0x0a, 0x0cf9);
  41         outb(0x0e, 0x0cf9);
  42 }
  43
  44 static void soft_reset(void)
  45 {
  46         set_bios_reset();
  47 #if 1
  48         /* link reset */
  49         outb(0x02, 0x0cf9);
  50         outb(0x06, 0x0cf9);
  51 #endif
  52 }
  53
  54 static void memreset_setup(void)
  55 {
  56 }
  57
  58 static void memreset(int controllers, const struct mem_controller *ctrl)
  59 {
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66
  67 static inline int spd_read_byte(unsigned device, unsigned address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #define QRANK_DIMM_SUPPORT 1
  73
  74 #include "northbridge/amd/amdk8/raminit.c"
  75 #include "northbridge/amd/amdk8/coherent_ht.c"
  76 #include "sdram/generic_sdram.c"
  77
  78  /* tyan does not want the default */
  79 #include "resourcemap.c"
  80
  81 #define FIRST_CPU  1
  82 #define SECOND_CPU 1
  83 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  84
  85 #define CK804_NUM 1
  86 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  87 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  88
  89 static void main(unsigned long bist)
  90 {
  91         static const struct mem_controller cpu[] = {
  92 #if FIRST_CPU
  93                 {
  94                         .node_id = 0,
  95                         .f0 = PCI_DEV(0, 0x18, 0),
  96                         .f1 = PCI_DEV(0, 0x18, 1),
  97                         .f2 = PCI_DEV(0, 0x18, 2),
  98                         .f3 = PCI_DEV(0, 0x18, 3),
  99                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 100                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 101                 },
 102 #endif
 103 #if SECOND_CPU
 104                 {
 105                         .node_id = 1,
 106                         .f0 = PCI_DEV(0, 0x19, 0),
 107                         .f1 = PCI_DEV(0, 0x19, 1),
 108                         .f2 = PCI_DEV(0, 0x19, 2),
 109                         .f3 = PCI_DEV(0, 0x19, 3),
 110                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 111                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 112                 },
 113 #endif
 114         };
 115
 116         int needs_reset;
 117 #if CONFIG_LOGICAL_CPUS==1
 118         struct node_core_id id;
 119 #else
 120         unsigned nodeid;
 121 #endif
 122
 123         if (bist == 0) {
 124                 k8_init_and_stop_secondaries();
 125         }
 126
 127         // post_code(0x32);
 128
 129         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 130         uart_init();
 131         console_init();
 132
 133         /* Halt if there was a built in self test failure */
 134         report_bist_failure(bist);
 135
 136         setup_s2891_resource_map();
 137
 138         needs_reset = setup_coherent_ht_domain();
 139
 140         needs_reset |= ht_setup_chains_x();
 141
 142         needs_reset |= ck804_early_setup_x();
 143
 144         if (needs_reset) {
 145                 print_info("ht reset -\r\n");
 146                 soft_reset();
 147         }
 148
 149         enable_smbus();
 150
 151         memreset_setup();
 152         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 153
 154 }