src/mainboard/tyan/s2885/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include "lib/ramtest.c"
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57         /* nothing to do */
  58 }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #define QRANK_DIMM_SUPPORT 1
  66
  67 #include "northbridge/amd/amdk8/raminit.c"
  68 #include "northbridge/amd/amdk8/coherent_ht.c"
  69 #include "lib/generic_sdram.c"
  70
  71  /* tyan does not want the default */
  72 #include "resourcemap.c"
  73
  74 #if CONFIG_LOGICAL_CPUS==1
  75 #define SET_NB_CFG_54 1
  76 #endif
  77 #include "cpu/amd/dualcore/dualcore.c"
  78
  79
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  86 #include "northbridge/amd/amdk8/early_ht.c"
  87
  88 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  89 {
  90         static const uint16_t spd_addr [] = {
  91                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  92                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  93 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  94                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  95                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  96 #endif
  97         };
  98
  99         int needs_reset;
 100         unsigned bsp_apicid = 0;
 101
 102         struct mem_controller ctrl[8];
 103         unsigned nodes;
 104
 105         if (!cpu_init_detectedx && boot_cpu()) {
 106                 /* Nothing special needs to be done to find bus 0 */
 107                 /* Allow the HT devices to be found */
 108
 109                 enumerate_ht_chain();
 110
 111                 /* Setup the amd8111 */
 112                 amd8111_enable_rom();
 113         }
 114
 115         if (bist == 0) {
 116                 bsp_apicid = init_cpus(cpu_init_detectedx);
 117         }
 118
 119 //      post_code(0x32);
 120
 121         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 122         uart_init();
 123         console_init();
 124
 125 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 126
 127         /* Halt if there was a built in self test failure */
 128         report_bist_failure(bist);
 129
 130         setup_s2885_resource_map();
 131 #if 0
 132         dump_pci_device(PCI_DEV(0, 0x18, 0));
 133         dump_pci_device(PCI_DEV(0, 0x19, 0));
 134 #endif
 135
 136         needs_reset = setup_coherent_ht_domain();
 137
 138         wait_all_core0_started();
 139 #if CONFIG_LOGICAL_CPUS==1
 140         // It is said that we should start core1 after all core0 launched
 141         start_other_cores();
 142         wait_all_other_cores_started(bsp_apicid);
 143 #endif
 144
 145         needs_reset |= ht_setup_chains_x();
 146
 147         if (needs_reset) {
 148                 print_info("ht reset -\n");
 149                 soft_reset();
 150         }
 151
 152         allow_all_aps_stop(bsp_apicid);
 153
 154         nodes = get_nodes();
 155         //It's the time to set ctrl now;
 156         fill_mem_ctrl(nodes, ctrl, spd_addr);
 157
 158         enable_smbus();
 159
 160         memreset_setup();
 161         sdram_initialize(nodes, ctrl);
 162
 163 #if 0
 164         dump_pci_devices();
 165 #endif
 166
 167         post_cache_as_ram();
 168
 169 }
 170