src/mainboard/tyan/s2885/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #if CONFIG_USE_INIT == 0
  24 #include "lib/memcpy.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  40
  41 static void memreset_setup(void)
  42 {
  43    if (is_cpu_pre_c0()) {
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  45    }
  46    else {
  47         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  48    }
  49         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54    if (is_cpu_pre_c0()) {
  55         udelay(800);
  56         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  57         udelay(90);
  58    }
  59 }
  60
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63         /* nothing to do */
  64 }
  65
  66 static inline int spd_read_byte(unsigned device, unsigned address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #define K8_4RANK_DIMM_SUPPORT 1
  72
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "sdram/generic_sdram.c"
  76
  77  /* tyan does not want the default */
  78 #include "resourcemap.c"
  79
  80 #if CONFIG_LOGICAL_CPUS==1
  81 #define SET_NB_CFG_54 1
  82 #endif
  83 #include "cpu/amd/dualcore/dualcore.c"
  84
  85
  86 #include "cpu/amd/car/copy_and_run.c"
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92
  93 #if USE_FALLBACK_IMAGE == 1
  94
  95 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  96 #include "northbridge/amd/amdk8/early_ht.c"
  97
  98 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
  99 {
 100         unsigned last_boot_normal_x = last_boot_normal();
 101
 102         /* Is this a cpu only reset? or Is this a secondary cpu? */
 103         if ((cpu_init_detectedx) || (!boot_cpu())) {
 104                 if (last_boot_normal_x) {
 105                         goto normal_image;
 106                 } else {
 107                         goto fallback_image;
 108                 }
 109         }
 110
 111         /* Nothing special needs to be done to find bus 0 */
 112         /* Allow the HT devices to be found */
 113
 114         enumerate_ht_chain();
 115
 116         amd8111_enable_rom();
 117
 118         /* Is this a deliberate reset by the bios */
 119         if (bios_reset_detected() && last_boot_normal_x) {
 120                 goto normal_image;
 121         }
 122         /* This is the primary cpu how should I boot? */
 123         else if (do_normal_boot()) {
 124                 goto normal_image;
 125         }
 126         else {
 127                 goto fallback_image;
 128         }
 129  normal_image:
 130         __asm__ volatile ("jmp __normal_image"
 131                 : /* outputs */
 132                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 133                 );
 134
 135  fallback_image:
 136         ;
 137 }
 138 #endif
 139
 140 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 141
 142 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 143 {
 144
 145 #if USE_FALLBACK_IMAGE == 1
 146         failover_process(bist, cpu_init_detectedx);
 147 #endif
 148         real_main(bist, cpu_init_detectedx);
 149
 150 }
 151
 152 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 153 {
 154         static const uint16_t spd_addr [] = {
 155                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 156                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 157 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 158                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 159                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 160 #endif
 161         };
 162
 163         int needs_reset;
 164         unsigned bsp_apicid = 0;
 165
 166         struct mem_controller ctrl[8];
 167         unsigned nodes;
 168
 169         if (bist == 0) {
 170                 bsp_apicid = init_cpus(cpu_init_detectedx);
 171         }
 172
 173
 174         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 175         uart_init();
 176         console_init();
 177
 178         /* Halt if there was a built in self test failure */
 179         report_bist_failure(bist);
 180
 181         setup_s2885_resource_map();
 182
 183         needs_reset = setup_coherent_ht_domain();
 184
 185 #if CONFIG_LOGICAL_CPUS==1
 186         // It is said that we should start core1 after all core0 launched
 187         wait_all_core0_started();
 188         start_other_cores();
 189 #endif
 190
 191         wait_all_aps_started(bsp_apicid);
 192
 193         needs_reset |= ht_setup_chains_x();
 194
 195         if (needs_reset) {
 196                 print_info("ht reset -\r\n");
 197                 soft_reset();
 198         }
 199
 200
 201         allow_all_aps_stop(bsp_apicid);
 202
 203         nodes = get_nodes();
 204         //It's the time to set ctrl now;
 205         fill_mem_ctrl(nodes, ctrl, spd_addr);
 206
 207         enable_smbus();
 208
 209         memreset_setup();
 210         sdram_initialize(nodes, ctrl);
 211
 212         post_cache_as_ram();
 213
 214 }