2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
45 if HAVE_MP_TABLE object mptable.o end
46 if HAVE_PIRQ_TABLE object irq_tables.o end
53 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
54 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
60 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
61 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
62 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
63 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
73 depends "$(MAINBOARD)/failover.c ./romcc"
74 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
77 makerule ./failover.inc
78 depends "$(MAINBOARD)/failover.c ./romcc"
79 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
83 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
84 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
87 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
88 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
93 ## Build our 16 bit and 32 bit linuxBIOS entry code
96 mainboardinit cpu/x86/16bit/entry16.inc
97 ldscript /cpu/x86/16bit/entry16.lds
100 mainboardinit cpu/x86/32bit/entry32.inc
104 ldscript /cpu/x86/32bit/entry32.lds
108 ldscript /cpu/amd/car/cache_as_ram.lds
113 ## Build our reset vector (This is where linuxBIOS is entered)
115 if USE_FALLBACK_IMAGE
116 mainboardinit cpu/x86/16bit/reset16.inc
117 ldscript /cpu/x86/16bit/reset16.lds
119 mainboardinit cpu/x86/32bit/reset32.inc
120 ldscript /cpu/x86/32bit/reset32.lds
125 ### Should this be in the northbridge code?
126 mainboardinit arch/i386/lib/cpu_reset.inc
130 ## Include an id string (For safe flashing)
132 mainboardinit arch/i386/lib/id.inc
133 ldscript /arch/i386/lib/id.lds
137 ## Setup Cache-As-Ram
139 mainboardinit cpu/amd/car/cache_as_ram.inc
143 ### This is the early phase of linuxBIOS startup
144 ### Things are delicate and we test to see if we should
145 ### failover to another image.
147 if USE_FALLBACK_IMAGE
149 ldscript /arch/i386/lib/failover.lds
151 ldscript /arch/i386/lib/failover.lds
152 mainboardinit ./failover.inc
157 ### O.k. We aren't just an intermediary anymore!
168 mainboardinit ./auto.inc
176 mainboardinit cpu/x86/fpu/enable_fpu.inc
177 mainboardinit cpu/x86/mmx/enable_mmx.inc
178 mainboardinit cpu/x86/sse/enable_sse.inc
179 mainboardinit ./auto.inc
180 mainboardinit cpu/x86/sse/disable_sse.inc
181 mainboardinit cpu/x86/mmx/disable_mmx.inc
186 ## Include the secondary Configuration files
192 # sample config for tyan/s2885
193 chip northbridge/amd/amdk8/root_complex
194 device apic_cluster 0 on
195 chip cpu/amd/socket_940
199 device pci_domain 0 on
200 chip northbridge/amd/amdk8
201 device pci 18.0 on # LDT0
202 chip southbridge/amd/amd8151
203 # the on/off keyword is mandatory
204 device pci 0.0 on end
205 device pci 1.0 on end
208 device pci 18.0 on end # LDT1
209 device pci 18.0 on # northbridge
210 # devices on link 2, link 2 == LDT 2
211 chip southbridge/amd/amd8131
212 # the on/off keyword is mandatory
214 chip drivers/pci/onboard
215 device pci 9.0 on end # broadcom 5703
218 device pci 0.1 on end
219 device pci 1.0 on end
220 device pci 1.1 on end
222 chip southbridge/amd/amd8111
223 # this "device pci 0.0" is the parent the next one
226 device pci 0.0 on end
227 device pci 0.1 on end
228 device pci 0.2 off end
229 device pci 1.0 off end
230 chip drivers/pci/onboard
231 device pci b.0 on end # SiI 3114
235 chip superio/winbond/w83627hf
236 device pnp 2e.0 on # Floppy
241 device pnp 2e.1 off # Parallel Port
245 device pnp 2e.2 on # Com1
249 device pnp 2e.3 on # Com2
253 device pnp 2e.5 on # Keyboard
259 device pnp 2e.6 off # CIR
262 device pnp 2e.7 off # GAME_MIDI_GIPO1
267 device pnp 2e.8 off end # GPIO2
268 device pnp 2e.9 off end # GPIO3
269 device pnp 2e.a off end # ACPI
270 device pnp 2e.b on # HW Monitor
276 device pci 1.1 on end
277 device pci 1.2 on end
279 chip drivers/generic/generic #dimm 0-0-0
282 chip drivers/generic/generic #dimm 0-0-1
285 chip drivers/generic/generic #dimm 0-1-0
288 chip drivers/generic/generic #dimm 0-1-1
291 chip drivers/generic/generic #dimm 1-0-0
294 chip drivers/generic/generic #dimm 1-0-1
297 chip drivers/generic/generic #dimm 1-1-0
300 chip drivers/generic/generic #dimm 1-1-1
304 device pci 1.5 on end
305 device pci 1.6 off end
306 register "ide0_enable" = "1"
307 register "ide1_enable" = "1"
309 end # device pci 18.0
311 device pci 18.1 on end
312 device pci 18.2 on end
313 device pci 18.3 on end
318 # chip drivers/generic/debug
319 # device pnp 0.0 off end
320 # device pnp 0.1 off end
321 # device pnp 0.2 off end
322 # device pnp 0.3 off end
323 # device pnp 0.4 off end
324 # device pnp 0.5 on end