src/mainboard/tyan/s2882/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include <console/console.h>
  13 #include "lib/ramtest.c"
  14
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  35
  36 static void memreset_setup(void)
  37 {
  38    if (is_cpu_pre_c0()) {
  39         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  40    }
  41    else {
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  43    }
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49    if (is_cpu_pre_c0()) {
  50         udelay(800);
  51         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  52         udelay(90);
  53    }
  54 }
  55
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58         /* nothing to do */
  59 }
  60
  61 static inline int spd_read_byte(unsigned device, unsigned address)
  62 {
  63         return smbus_read_byte(device, address);
  64 }
  65
  66 #define QRANK_DIMM_SUPPORT 1
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "northbridge/amd/amdk8/resourcemap.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72
  73 #if CONFIG_LOGICAL_CPUS==1
  74 #define SET_NB_CFG_54 1
  75 #endif
  76 #include "cpu/amd/dualcore/dualcore.c"
  77
  78 #define FIRST_CPU  1
  79 #define SECOND_CPU 1
  80 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  81
  82
  83
  84 #include "cpu/amd/car/post_cache_as_ram.c"
  85
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87
  88 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  89 #include "northbridge/amd/amdk8/early_ht.c"
  90
  91 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  92 {
  93         static const struct mem_controller cpu[] = {
  94                 {
  95                         .node_id = 0,
  96                         .f0 = PCI_DEV(0, 0x18, 0),
  97                         .f1 = PCI_DEV(0, 0x18, 1),
  98                         .f2 = PCI_DEV(0, 0x18, 2),
  99                         .f3 = PCI_DEV(0, 0x18, 3),
 100                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 101                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 102                 },
 103 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 104                 {
 105                         .node_id = 1,
 106                         .f0 = PCI_DEV(0, 0x19, 0),
 107                         .f1 = PCI_DEV(0, 0x19, 1),
 108                         .f2 = PCI_DEV(0, 0x19, 2),
 109                         .f3 = PCI_DEV(0, 0x19, 3),
 110                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 111                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 112                 },
 113 #endif
 114         };
 115
 116         int needs_reset;
 117
 118         if (!cpu_init_detectedx && boot_cpu()) {
 119                 /* Nothing special needs to be done to find bus 0 */
 120                 /* Allow the HT devices to be found */
 121
 122                 enumerate_ht_chain();
 123
 124                 amd8111_enable_rom();
 125         }
 126
 127         if (bist == 0) {
 128                 init_cpus(cpu_init_detectedx);
 129         }
 130
 131
 132         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 133         uart_init();
 134         console_init();
 135
 136         /* Halt if there was a built in self test failure */
 137         report_bist_failure(bist);
 138
 139         setup_default_resource_map();
 140
 141         needs_reset = setup_coherent_ht_domain();
 142
 143 #if CONFIG_LOGICAL_CPUS==1
 144         // It is said that we should start core1 after all core0 launched
 145         start_other_cores();
 146 #endif
 147         // automatically set that for you, but you might meet tight space
 148         needs_reset |= ht_setup_chains_x();
 149
 150         if (needs_reset) {
 151                 print_info("ht reset -\n");
 152                 soft_reset();
 153         }
 154
 155         enable_smbus();
 156
 157         memreset_setup();
 158         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 159
 160         post_cache_as_ram();
 161
 162 }
 163