1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
8 #if CONFIG_LOGICAL_CPUS==1
9 #include <cpu/amd/multicore.h>
12 static unsigned node_link_to_bus(unsigned node, unsigned link)
17 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
21 for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
26 config_map = pci_read_config32(dev, reg);
27 if ((config_map & 3) != 3) {
30 dst_node = (config_map >> 4) & 7;
31 dst_link = (config_map >> 8) & 3;
32 bus_base = (config_map >> 16) & 0xff;
34 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
35 dst_node, dst_link, bus_base,
38 if ((dst_node == node) && (dst_link == link))
46 static void *smp_write_config_table(void *v)
48 struct mp_config_table *mc;
50 unsigned char bus_chain_0;
51 unsigned char bus_8131_1;
52 unsigned char bus_8131_2;
53 unsigned char bus_8111_1;
56 unsigned apicid_8131_1;
57 unsigned apicid_8131_2;
59 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
61 mptable_init(mc, "S2882 ", LAPIC_ADDR);
63 smp_write_processors(mc);
68 bus_chain_0 = node_link_to_bus(0, 0);
69 if (bus_chain_0 == 0) {
70 printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n");
75 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
77 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
80 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
85 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
87 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
91 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
96 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
98 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
102 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
107 mptable_write_buses(mc, NULL, &bus_isa);
109 /*I/O APICs: APIC ID Version State Address*/
110 #if CONFIG_LOGICAL_CPUS==1
111 apicid_base = get_apicid_base(3);
113 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
115 apicid_8111 = apicid_base+0;
116 apicid_8131_1 = apicid_base+1;
117 apicid_8131_2 = apicid_base+2;
119 smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
122 struct resource *res;
123 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
125 res = find_resource(dev, PCI_BASE_ADDRESS_0);
127 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
130 dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
132 res = find_resource(dev, PCI_BASE_ADDRESS_0);
134 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
140 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
142 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
150 //On Board ATI Display Adapter
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
161 //Onboard SI Serial ATA
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
164 //Onboard Intel 82551 10/100M NIC
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
177 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
182 //Onboard adaptec scsi
183 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
192 //Slot 1 PCI-X 133/100/66
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
194 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
196 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
198 //Slot 2 PCI-X 133/100/66
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
200 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
202 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
205 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
206 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
207 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
208 /* There is no extension information... */
210 /* Compute the checksums */
211 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
212 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
213 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
214 mc, smp_next_mpe_entry(mc));
215 return smp_next_mpe_entry(mc);
218 unsigned long write_smp_table(unsigned long addr)
221 v = smp_write_floating_table(addr);
222 return (unsigned long)smp_write_config_table(v);