src/mainboard/tyan/s2880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42
  43 #dir /drivers/si/3114
  44
  45 if HAVE_MP_TABLE object mptable.o end
  46 if HAVE_PIRQ_TABLE object irq_tables.o end
  47 object reset.o
  48
  49 if USE_DCACHE_RAM
  50
  51 if CONFIG_USE_INIT
  52
  53 makerule ./auto.o
  54         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  55         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  56 end
  57
  58 else
  59
  60 makerule ./auto.inc
  61         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  62         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  63         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  64         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  65 end
  66
  67 end
  68 else
  69
  70 ##
  71 ## Romcc output
  72 ##
  73 makerule ./failover.E
  74         depends "$(MAINBOARD)/failover.c ./romcc"
  75         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  76 end
  77
  78 makerule ./failover.inc
  79         depends "$(MAINBOARD)/failover.c ./romcc"
  80         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  81 end
  82
  83 makerule ./auto.E
  84         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  85         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  86 end
  87 makerule ./auto.inc
  88         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  89         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  90 end
  91
  92 end
  93 ##
  94 ## Build our 16 bit and 32 bit linuxBIOS entry code
  95 ##
  96 mainboardinit cpu/x86/16bit/entry16.inc
  97 mainboardinit cpu/x86/32bit/entry32.inc
  98 ldscript /cpu/x86/16bit/entry16.lds
  99 if USE_DCACHE_RAM
 100         if CONFIG_USE_INIT
 101                 ldscript /cpu/x86/32bit/entry32.lds
 102         end
 103
 104         if CONFIG_USE_INIT
 105                 ldscript      /cpu/amd/car/cache_as_ram.lds
 106         end
 107 end
 108
 109 ##
 110 ## Build our reset vector (This is where linuxBIOS is entered)
 111 ##
 112 if USE_FALLBACK_IMAGE
 113         mainboardinit cpu/x86/16bit/reset16.inc
 114         ldscript /cpu/x86/16bit/reset16.lds
 115 else
 116         mainboardinit cpu/x86/32bit/reset32.inc
 117         ldscript /cpu/x86/32bit/reset32.lds
 118 end
 119
 120 if USE_DCACHE_RAM
 121 else
 122 ### Should this be in the northbridge code?
 123 mainboardinit arch/i386/lib/cpu_reset.inc
 124 end
 125
 126 ##
 127 ## Include an id string (For safe flashing)
 128 ##
 129 mainboardinit arch/i386/lib/id.inc
 130 ldscript /arch/i386/lib/id.lds
 131
 132 if USE_DCACHE_RAM
 133 ##
 134 ## Setup Cache-As-Ram
 135 ##
 136 mainboardinit cpu/amd/car/cache_as_ram.inc
 137 end
 138
 139 ###
 140 ### This is the early phase of linuxBIOS startup
 141 ### Things are delicate and we test to see if we should
 142 ### failover to another image.
 143 ###
 144 if USE_FALLBACK_IMAGE
 145 if USE_DCACHE_RAM
 146        ldscript /arch/i386/lib/failover.lds
 147 else
 148        ldscript /arch/i386/lib/failover.lds
 149         mainboardinit ./failover.inc
 150 end
 151 end
 152
 153 ###
 154 ### O.k. We aren't just an intermediary anymore!
 155 ###
 156
 157 ##
 158 ## Setup RAM
 159 ##
 160 if USE_DCACHE_RAM
 161
 162 if CONFIG_USE_INIT
 163 initobject auto.o
 164 else
 165 mainboardinit ./auto.inc
 166 end
 167
 168 else
 169
 170 ##
 171 ## Setup RAM
 172 ##
 173 mainboardinit cpu/x86/fpu/enable_fpu.inc
 174 mainboardinit cpu/x86/mmx/enable_mmx.inc
 175 mainboardinit cpu/x86/sse/enable_sse.inc
 176 mainboardinit ./auto.inc
 177 mainboardinit cpu/x86/sse/disable_sse.inc
 178 mainboardinit cpu/x86/mmx/disable_mmx.inc
 179
 180 end
 181
 182 ##
 183 ## Include the secondary Configuration files
 184 ##
 185 if CONFIG_CHIP_NAME
 186         config chip.h
 187 end
 188
 189 # sample config for tyan/s2880
 190 chip northbridge/amd/amdk8/root_complex
 191         device apic_cluster 0 on
 192                 chip cpu/amd/socket_940
 193                         device apic 0 on end
 194                 end
 195         end
 196         device pci_domain 0 on
 197                 chip northbridge/amd/amdk8
 198                         device pci 18.0 on #  northbridge
 199                                 #  devices on link 0, link 0 == LDT 0
 200                                 chip southbridge/amd/amd8131
 201                                         # the on/off keyword is mandatory
 202                                         device pci 0.0 on
 203                                                 chip drivers/pci/onboard
 204                                                         device pci 9.0 on end #broadcom
 205                                                         device pci 9.1 on end
 206                                                 end
 207 #                                                chip drivers/lsi/53c1030
 208 #                                                        device pci a.0 on end
 209 #                                                        device pci a.1 on end
 210 #                                                        register "fw_address" = "0xfff8c000"
 211 #                                                end
 212                                         end
 213                                         device pci 0.1 on end
 214                                         device pci 1.0 on end
 215                                         device pci 1.1 on end
 216                                 end
 217                                 chip southbridge/amd/amd8111
 218                                         # this "device pci 0.0" is the parent the next one
 219                                         # PCI bridge
 220                                         device pci 0.0 on
 221                                                 device pci 0.0 on end
 222                                                 device pci 0.1 on end
 223                                                 device pci 0.2 off end
 224                                                 device pci 1.0 off end
 225                                                 chip drivers/pci/onboard
 226                                                         device pci 5.0 on end #some sata
 227                                                 end
 228                                                 chip drivers/pci/onboard
 229                                                         device pci 6.0 on end #adti
 230                                                         register "rom_address" = "0xfff80000"
 231                                                 end
 232                                         end
 233                                         device pci 1.0 on
 234                                                 chip superio/winbond/w83627hf
 235                                                         device pnp 2e.0 on #  Floppy
 236                                                                 io 0x60 = 0x3f0
 237                                                                 irq 0x70 = 6
 238                                                                 drq 0x74 = 2
 239                                                         end
 240                                                         device pnp 2e.1 off #  Parallel Port
 241                                                                 io 0x60 = 0x378
 242                                                                 irq 0x70 = 7
 243                                                         end
 244                                                         device pnp 2e.2 on #  Com1
 245                                                                 io 0x60 = 0x3f8
 246                                                                 irq 0x70 = 4
 247                                                         end
 248                                                         device pnp 2e.3 off #  Com2
 249                                                                 io 0x60 = 0x2f8
 250                                                                 irq 0x70 = 3
 251                                                         end
 252                                                         device pnp 2e.5 on #  Keyboard
 253                                                                 io 0x60 = 0x60
 254                                                                 io 0x62 = 0x64
 255                                                                 irq 0x70 = 1
 256                                                                 irq 0x72 = 12
 257                                                         end
 258                                                         device pnp 2e.6 off #  CIR
 259                                                                 io 0x60 = 0x100
 260                                                         end
 261                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 262                                                                 io 0x60 = 0x220
 263                                                                 io 0x62 = 0x300
 264                                                                 irq 0x70 = 9
 265                                                         end
 266                                                         device pnp 2e.8 off end #  GPIO2
 267                                                         device pnp 2e.9 off end #  GPIO3
 268                                                         device pnp 2e.a off end #  ACPI
 269                                                         device pnp 2e.b on #  HW Monitor
 270                                                                 io 0x60 = 0x290
 271                                                                 irq 0x70 = 5
 272                                                         end
 273                                                 end
 274                                         end
 275                                         device pci 1.1 on end
 276                                         device pci 1.2 on end
 277                                         device pci 1.3 on end
 278                                         device pci 1.5 off end
 279                                         device pci 1.6 off end
 280                                         register "ide0_enable" = "1"
 281                                         register "ide1_enable" = "1"
 282                                 end
 283                         end #  device pci 18.0
 284
 285                         device pci 18.0 on end
 286                         device pci 18.0 on end
 287
 288                         device pci 18.1 on end
 289                         device pci 18.2 on end
 290                         device pci 18.3 on end
 291                 end
 292         end
 293 end
 294