src/mainboard/tyan/s2850/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "console/console.c"
  14 #include "lib/ramtest.c"
  15
  16 #if 0
  17 static void post_code(uint8_t value) {
  18 #if 1
  19         int i;
  20         for(i=0;i<0x80000;i++) {
  21                 outb(value, 0x80);
  22         }
  23 #endif
  24 }
  25 #endif
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36 #include "northbridge/amd/amdk8/debug.c"
  37 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  38
  39 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  40 #include "cpu/x86/bist.h"
  41
  42 #include "northbridge/amd/amdk8/setup_resource_map.c"
  43
  44 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  45
  46 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  47
  48 static void memreset_setup(void)
  49 {
  50    if (is_cpu_pre_c0()) {
  51         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  52    }
  53    else {
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  55    }
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61    if (is_cpu_pre_c0()) {
  62         udelay(800);
  63         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  64         udelay(90);
  65    }
  66 }
  67
  68 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  69 {
  70         /* nothing to do */
  71 }
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78 #include "northbridge/amd/amdk8/raminit.c"
  79 #include "northbridge/amd/amdk8/resourcemap.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "lib/generic_sdram.c"
  82
  83 #if CONFIG_LOGICAL_CPUS==1
  84 #define SET_NB_CFG_54 1
  85 #endif
  86 #include "cpu/amd/dualcore/dualcore.c"
  87
  88 #include "cpu/amd/car/copy_and_run.c"
  89
  90 #include "cpu/amd/car/post_cache_as_ram.c"
  91
  92 #include "cpu/amd/model_fxx/init_cpus.c"
  93
  94 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  95 #include "northbridge/amd/amdk8/early_ht.c"
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         static const struct mem_controller cpu[] = {
 100                 {
 101                         .node_id = 0,
 102                         .f0 = PCI_DEV(0, 0x18, 0),
 103                         .f1 = PCI_DEV(0, 0x18, 1),
 104                         .f2 = PCI_DEV(0, 0x18, 2),
 105                         .f3 = PCI_DEV(0, 0x18, 3),
 106                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 107                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 108                 },
 109         };
 110
 111         int needs_reset;
 112
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0 */
 115                 /* Allow the HT devices to be found */
 116
 117                 enumerate_ht_chain();
 118
 119                 /* Setup the amd8111 */
 120                 amd8111_enable_rom();
 121         }
 122
 123         if (bist == 0) {
 124                 init_cpus(cpu_init_detectedx);
 125         }
 126
 127 //      post_code(0x32);
 128
 129         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 130         uart_init();
 131         console_init();
 132
 133         /* Halt if there was a built in self test failure */
 134         report_bist_failure(bist);
 135
 136         setup_default_resource_map();
 137
 138         needs_reset = setup_coherent_ht_domain();
 139
 140 #if CONFIG_LOGICAL_CPUS==1
 141         // It is said that we should start core1 after all core0 launched
 142         start_other_cores();
 143 #endif
 144         needs_reset |= ht_setup_chains_x();
 145
 146         if (needs_reset) {
 147                 print_info("ht reset -\n");
 148                 soft_reset();
 149         }
 150
 151         enable_smbus();
 152
 153         memreset_setup();
 154         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 155
 156         post_cache_as_ram();
 157 }
 158