src/mainboard/tyan/s2850/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <stdlib.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #if 0
  18 static void post_code(uint8_t value) {
  19 #if 1
  20         int i;
  21         for(i=0;i<0x80000;i++) {
  22                 outb(value, 0x80);
  23         }
  24 #endif
  25 }
  26 #endif
  27
  28 #include <cpu/amd/model_fxx_rev.h>
  29 #include "northbridge/amd/amdk8/incoherent_ht.c"
  30 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33 #include "lib/delay.c"
  34
  35 #if CONFIG_USE_INIT == 0
  36 #include "lib/memcpy.c"
  37 #endif
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  43
  44 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  50
  51 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  52
  53 static void memreset_setup(void)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  57    }
  58    else {
  59         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  60    }
  61         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  62 }
  63
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66    if (is_cpu_pre_c0()) {
  67         udelay(800);
  68         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  69         udelay(90);
  70    }
  71 }
  72
  73 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  74 {
  75         /* nothing to do */
  76 }
  77
  78 static inline int spd_read_byte(unsigned device, unsigned address)
  79 {
  80         return smbus_read_byte(device, address);
  81 }
  82
  83 #include "northbridge/amd/amdk8/raminit.c"
  84 #include "northbridge/amd/amdk8/resourcemap.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "sdram/generic_sdram.c"
  87
  88 #if CONFIG_LOGICAL_CPUS==1
  89 #define SET_NB_CFG_54 1
  90 #endif
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #include "cpu/amd/car/copy_and_run.c"
  94
  95 #include "cpu/amd/car/post_cache_as_ram.c"
  96
  97 #include "cpu/amd/model_fxx/init_cpus.c"
  98
  99
 100 #if USE_FALLBACK_IMAGE == 1
 101
 102 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 103 #include "northbridge/amd/amdk8/early_ht.c"
 104
 105 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 106 {
 107         unsigned last_boot_normal_x = last_boot_normal();
 108
 109         /* Is this a cpu only reset? or Is this a secondary cpu? */
 110         if ((cpu_init_detectedx) || (!boot_cpu())) {
 111                 if (last_boot_normal_x) {
 112                         goto normal_image;
 113                 } else {
 114                         goto fallback_image;
 115                 }
 116         }
 117
 118         /* Nothing special needs to be done to find bus 0 */
 119         /* Allow the HT devices to be found */
 120
 121         enumerate_ht_chain();
 122
 123         /* Setup the amd8111 */
 124         amd8111_enable_rom();
 125
 126         /* Is this a deliberate reset by the bios */
 127 //        post_code(0x22);
 128         if (bios_reset_detected() && last_boot_normal_x) {
 129                 goto normal_image;
 130         }
 131         /* This is the primary cpu how should I boot? */
 132         else if (do_normal_boot()) {
 133                 goto normal_image;
 134         }
 135         else {
 136                 goto fallback_image;
 137         }
 138  normal_image:
 139 //        post_code(0x23);
 140         __asm__ volatile ("jmp __normal_image"
 141                 : /* outputs */
 142                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 143                 );
 144
 145  fallback_image:
 146 //        post_code(0x25);
 147         ;
 148 }
 149 #endif
 150
 151 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 152
 153 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 154 {
 155
 156 #if USE_FALLBACK_IMAGE == 1
 157         failover_process(bist, cpu_init_detectedx);
 158 #endif
 159         real_main(bist, cpu_init_detectedx);
 160
 161 }
 162
 163 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 164 {
 165         static const struct mem_controller cpu[] = {
 166                 {
 167                         .node_id = 0,
 168                         .f0 = PCI_DEV(0, 0x18, 0),
 169                         .f1 = PCI_DEV(0, 0x18, 1),
 170                         .f2 = PCI_DEV(0, 0x18, 2),
 171                         .f3 = PCI_DEV(0, 0x18, 3),
 172                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 173                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 174                 },
 175         };
 176
 177         int needs_reset;
 178
 179         if (bist == 0) {
 180                 init_cpus(cpu_init_detectedx);
 181         }
 182
 183 //      post_code(0x32);
 184
 185         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 186         uart_init();
 187         console_init();
 188
 189         /* Halt if there was a built in self test failure */
 190         report_bist_failure(bist);
 191
 192         setup_default_resource_map();
 193
 194         needs_reset = setup_coherent_ht_domain();
 195
 196 #if CONFIG_LOGICAL_CPUS==1
 197         // It is said that we should start core1 after all core0 launched
 198         start_other_cores();
 199 #endif
 200         needs_reset |= ht_setup_chains_x();
 201
 202         if (needs_reset) {
 203                 print_info("ht reset -\r\n");
 204                 soft_reset();
 205         }
 206
 207         enable_smbus();
 208
 209         memreset_setup();
 210         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 211
 212         post_cache_as_ram();
 213 }