6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
13 #include "pc80/serial.c"
14 #include "arch/i386/lib/console.c"
15 #include "ram/ramtest.c"
18 static void post_code(uint8_t value) {
21 for(i=0;i<0x80000;i++) {
28 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
29 #include "northbridge/intel/e7501/raminit.h"
31 #include "cpu/x86/lapic/boot_cpu.c"
32 #include "northbridge/intel/e7501/debug.c"
33 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
35 #include "cpu/x86/mtrr/earlymtrr.c"
36 #include "cpu/x86/bist.h"
38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 static void hard_reset(void)
47 static void soft_reset(void)
56 static void memreset_setup(void)
60 static void memreset(int controllers, const struct mem_controller *ctrl)
64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
69 static inline int spd_read_byte(unsigned device, unsigned address)
71 return smbus_read_byte(device, address);
75 #include "northbridge/intel/e7501/raminit.c"
76 #include "northbridge/intel/e7501/reset_test.c"
77 #include "sdram/generic_sdram.c"
80 #include "cpu/x86/car/copy_and_run.c"
82 #if CONFIG_USE_FALLBACK_IMAGE == 1
84 #include "southbridge/intel/i82801er/cmos_failover.c"
86 void real_main(unsigned long bist);
88 void amd64_main(unsigned long bist)
90 /* Is this a deliberate reset by the bios */
92 if (bios_reset_detected() && last_boot_normal()) {
95 /* This is the primary cpu how should I boot? */
98 if (do_normal_boot()) {
107 __asm__ volatile ("jmp __normal_image"
109 : "a" (bist) /* inputs */
114 //CPU reset will reset memtroller ???
115 asm volatile ("jmp __cpu_reset"
117 : "a"(bist) /* inputs */
125 void real_main(unsigned long bist)
127 void amd64_main(unsigned long bist)
130 static const struct mem_controller memctrl[] = {
132 .d0 = PCI_DEV(0, 0, 0),
133 .d0f1 = PCI_DEV(0, 0, 1),
134 .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
135 .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
139 unsigned cpu_reset = 0;
143 // early_mtrr_init();
150 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
154 /* Halt if there was a built in self test failure */
155 report_bist_failure(bist);
157 // setup_s2735_resource_map();
159 if(bios_reset_detected()) {
166 dump_spd_registers(&memctrl[0]);
169 dump_smbus_registers();
173 sdram_initialize(1, memctrl);
180 dump_pci_device(PCI_DEV(0, 0, 0));
186 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
193 printk_debug("v_esp=%08x\r\n", v_esp);
195 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
205 printk_debug("cpu_reset = %08x\r\n",cpu_reset);
207 print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
211 print_debug("Clearing initial memory region: ");
213 print_debug("No cache as ram now - ");
215 /* store cpu_reset to ebx */
222 #define CLEAR_FIRST_1M_RAM 1
223 #include "cpu/x86/car/cache_as_ram_post.c"
226 #undef CLEAR_FIRST_1M_RAM
227 #include "cpu/x86/car/cache_as_ram_post.c"
231 /* set new esp */ /* before CONFIG_RAMBASE */
234 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
238 unsigned new_cpu_reset;
240 /* get back cpu_reset from ebx */
243 :"=a" (new_cpu_reset)
246 /* We can not go back any more, we lost old stack data in cache as ram*/
247 if(new_cpu_reset==0) {
248 print_debug("Use Ram as Stack now - done\r\n");
251 print_debug("Use Ram as Stack now - \r\n");
254 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
256 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
259 #ifdef CONFIG_DEACTIVATE_CAR
260 print_debug("Deactivating CAR");
261 #include CONFIG_DEACTIVATE_CAR_FILE
262 print_debug(" - Done.\r\n");
264 /*copy and execute coreboot_ram */
265 copy_and_run(new_cpu_reset);
266 /* We will not return */
271 print_debug("should not be here -\r\n");