src/mainboard/tyan/s2735/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #if 0
  17 static void post_code(uint8_t value) {
  18 #if 1
  19         int i;
  20         for(i=0;i<0x80000;i++) {
  21                 outb(value, 0x80);
  22         }
  23 #endif
  24 }
  25 #endif
  26
  27 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
  28 #include "northbridge/intel/e7501/raminit.h"
  29
  30 #if CONFIG_USE_INIT == 0
  31 #include "lib/memcpy.c"
  32 #endif
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/intel/e7501/debug.c"
  36 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  37
  38 #include "cpu/x86/mtrr/earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  42
  43 static void hard_reset(void)
  44 {
  45         /* full reset */
  46         outb(0x0a, 0x0cf9);
  47         outb(0x0e, 0x0cf9);
  48 }
  49
  50 static void soft_reset(void)
  51 {
  52 #if 1
  53         /* link reset */
  54         outb(0x02, 0x0cf9);
  55         outb(0x06, 0x0cf9);
  56 #endif
  57 }
  58
  59 static void memreset_setup(void)
  60 {
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  68 {
  69         /* nothing to do */
  70 }
  71
  72 static inline int spd_read_byte(unsigned device, unsigned address)
  73 {
  74         return smbus_read_byte(device, address);
  75 }
  76
  77
  78 #include "northbridge/intel/e7501/raminit.c"
  79 #include "northbridge/intel/e7501/reset_test.c"
  80 #include "sdram/generic_sdram.c"
  81
  82
  83 #include "cpu/x86/car/copy_and_run.c"
  84
  85 #if USE_FALLBACK_IMAGE == 1
  86
  87 #include "southbridge/intel/i82801er/cmos_failover.c"
  88
  89 void real_main(unsigned long bist);
  90
  91 void amd64_main(unsigned long bist)
  92 {
  93         /* Is this a deliberate reset by the bios */
  94 //        post_code(0x22);
  95         if (bios_reset_detected() && last_boot_normal()) {
  96                 goto normal_image;
  97         }
  98         /* This is the primary cpu how should I boot? */
  99         else {
 100                 check_cmos_failed();
 101                 if (do_normal_boot()) {
 102                         goto normal_image;
 103                 }
 104                 else {
 105                         goto fallback_image;
 106                 }
 107         }
 108  normal_image:
 109 //        post_code(0x23);
 110         __asm__ volatile ("jmp __normal_image"
 111                 : /* outputs */
 112                 : "a" (bist) /* inputs */
 113                 );
 114  cpu_reset:
 115 //        post_code(0x24);
 116 #if 0
 117         //CPU reset will reset memtroller ???
 118         asm volatile ("jmp __cpu_reset"
 119                 : /* outputs */
 120                 : "a"(bist) /* inputs */
 121                 );
 122 #endif
 123
 124  fallback_image:
 125 //        post_code(0x25);
 126         real_main(bist);
 127 }
 128 void real_main(unsigned long bist)
 129 #else
 130 void amd64_main(unsigned long bist)
 131 #endif
 132 {
 133         static const struct mem_controller memctrl[] = {
 134                 {
 135                         .d0 = PCI_DEV(0, 0, 0),
 136                         .d0f1 = PCI_DEV(0, 0, 1),
 137                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
 138                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
 139                 },
 140         };
 141
 142         unsigned cpu_reset = 0;
 143
 144        if (bist == 0)
 145         {
 146 //              early_mtrr_init();
 147                 enable_lapic();
 148
 149         }
 150
 151 //      post_code(0x32);
 152
 153         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 154         uart_init();
 155         console_init();
 156
 157         /* Halt if there was a built in self test failure */
 158         report_bist_failure(bist);
 159
 160 //        setup_s2735_resource_map();
 161
 162         if(bios_reset_detected()) {
 163                 cpu_reset = 1;
 164                 goto cpu_reset_x;
 165         }
 166
 167         enable_smbus();
 168 #if 0
 169         dump_spd_registers(&memctrl[0]);
 170 #endif
 171 #if 0
 172         dump_smbus_registers();
 173 #endif
 174
 175         memreset_setup();
 176         sdram_initialize(1, memctrl);
 177
 178 #if 0
 179         dump_pci_devices();
 180 #endif
 181
 182 #if 1
 183         dump_pci_device(PCI_DEV(0, 0, 0));
 184 #endif
 185
 186
 187 #if 1
 188         {
 189                 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
 190                 unsigned v_esp;
 191                 __asm__ volatile (
 192                         "movl   %%esp, %0\n\t"
 193                         : "=a" (v_esp)
 194                 );
 195 #if CONFIG_USE_INIT
 196                 printk_debug("v_esp=%08x\r\n", v_esp);
 197 #else
 198                 print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
 199 #endif
 200         }
 201
 202 #endif
 203 #if 1
 204
 205 cpu_reset_x:
 206
 207 #if CONFIG_USE_INIT
 208         printk_debug("cpu_reset = %08x\r\n",cpu_reset);
 209 #else
 210         print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
 211 #endif
 212
 213         if(cpu_reset == 0) {
 214                 print_debug("Clearing initial memory region: ");
 215         }
 216         print_debug("No cache as ram now - ");
 217
 218         /* store cpu_reset to ebx */
 219         __asm__ volatile (
 220                 "movl %0, %%ebx\n\t"
 221                 ::"a" (cpu_reset)
 222         );
 223
 224         if(cpu_reset==0) {
 225 #define CLEAR_FIRST_1M_RAM 1
 226 #include "cpu/x86/car/cache_as_ram_post.c"
 227         }
 228         else {
 229 #undef CLEAR_FIRST_1M_RAM
 230 #include "cpu/x86/car/cache_as_ram_post.c"
 231         }
 232
 233         __asm__ volatile (
 234                 /* set new esp */ /* before _RAMBASE */
 235                 "subl   %0, %%ebp\n\t"
 236                 "subl   %0, %%esp\n\t"
 237                 ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
 238         );
 239
 240         {
 241                 unsigned new_cpu_reset;
 242
 243                 /* get back cpu_reset from ebx */
 244                 __asm__ volatile (
 245                         "movl %%ebx, %0\n\t"
 246                         :"=a" (new_cpu_reset)
 247                 );
 248
 249                 /* We can not go back any more, we lost old stack data in cache as ram*/
 250                 if(new_cpu_reset==0) {
 251                         print_debug("Use Ram as Stack now - done\r\n");
 252                 } else
 253                 {
 254                         print_debug("Use Ram as Stack now - \r\n");
 255                 }
 256 #if CONFIG_USE_INIT
 257                 printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
 258 #else
 259                 print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
 260 #endif
 261
 262                 /*copy and execute coreboot_ram */
 263                 copy_and_run(new_cpu_reset);
 264                 /* We will not return */
 265         }
 266 #endif
 267
 268
 269         print_debug("should not be here -\r\n");
 270
 271 }