2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_STREAM = 1
22 ## Compute where this copy of linuxBIOS will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
44 if HAVE_MP_TABLE object mptable.o end
45 if HAVE_PIRQ_TABLE object irq_tables.o end
52 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
53 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
59 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
60 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
61 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
62 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
72 depends "$(MAINBOARD)/failover.c ./romcc"
73 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
76 makerule ./failover.inc
77 depends "$(MAINBOARD)/failover.c ./romcc"
78 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
82 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
83 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
86 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
87 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
93 ## Build our 16 bit and 32 bit linuxBIOS entry code
95 mainboardinit cpu/x86/16bit/entry16.inc
96 mainboardinit cpu/x86/32bit/entry32.inc
97 ldscript /cpu/x86/16bit/entry16.lds
100 ldscript /cpu/x86/32bit/entry32.lds
104 ldscript /cpu/intel/car/cache_as_ram.lds
110 ## Build our reset vector (This is where linuxBIOS is entered)
112 if USE_FALLBACK_IMAGE
113 mainboardinit cpu/x86/16bit/reset16.inc
114 ldscript /cpu/x86/16bit/reset16.lds
116 mainboardinit cpu/x86/32bit/reset32.inc
117 ldscript /cpu/x86/32bit/reset32.lds
122 ### Should this be in the northbridge code?
123 mainboardinit arch/i386/lib/cpu_reset.inc
127 ## Include an id string (For safe flashing)
129 mainboardinit arch/i386/lib/id.inc
130 ldscript /arch/i386/lib/id.lds
134 ## Setup Cache-As-Ram
136 mainboardinit cpu/intel/car/cache_as_ram.inc
140 ### This is the early phase of linuxBIOS startup
141 ### Things are delicate and we test to see if we should
142 ### failover to another image.
144 if USE_FALLBACK_IMAGE
146 ldscript /arch/i386/lib/failover.lds
148 ldscript /arch/i386/lib/failover.lds
149 mainboardinit ./failover.inc
161 mainboardinit ./auto.inc
166 mainboardinit cpu/x86/fpu/enable_fpu.inc
167 mainboardinit cpu/x86/mmx/enable_mmx.inc
168 mainboardinit cpu/x86/sse/enable_sse.inc
169 mainboardinit ./auto.inc
170 mainboardinit cpu/x86/sse/disable_sse.inc
171 mainboardinit cpu/x86/mmx/disable_mmx.inc
176 ## Include the secondary Configuration files
183 # sample config for tyan/s2735
184 chip northbridge/intel/e7501
185 device pci_domain 0 on
186 device pci 0.0 on end
187 device pci 0.1 on end
189 chip southbridge/intel/i82870
190 device pci 1c.0 on end
192 chip drivers/pci/onboard
193 device pci 1.0 on end # intel lan
194 device pci 1.1 on end
197 device pci 1e.0 on end
198 device pci 1f.0 on end
201 device pci 6.0 on end
202 chip southbridge/intel/i82801er
203 device pci 1d.0 on end
204 device pci 1d.1 on end
205 device pci 1d.2 on end
206 device pci 1d.3 on end
207 device pci 1d.7 on end
209 chip drivers/pci/onboard
210 device pci 1.0 on end # intel lan 10/100
212 chip drivers/pci/onboard
213 device pci 2.0 on end # ati
217 chip superio/winbond/w83627hf
218 device pnp 2e.0 on # Floppy
223 device pnp 2e.1 off # Parallel Port
227 device pnp 2e.2 on # Com1
231 device pnp 2e.3 on # Com2
235 device pnp 2e.5 on # Keyboard
241 device pnp 2e.6 off # CIR
244 device pnp 2e.7 off # GAME_MIDI_GIPO1
249 device pnp 2e.8 off end # GPIO2
250 device pnp 2e.9 off end # GPIO3
251 device pnp 2e.a off end # ACPI
252 device pnp 2e.b on # HW Monitor
258 device pci 1f.1 off end
259 device pci 1f.2 on end
260 device pci 1f.3 on end
261 device pci 1f.5 off end
262 device pci 1f.6 off end
265 device apic_cluster 0 on
266 chip cpu/intel/socket_mPGA604_533Mhz
269 chip cpu/intel/socket_mPGA604_533Mhz