src/mainboard/tyan/s2735/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12 #
  13 #
  14 ###
  15 ### Set all of the defaults for an x86 architecture
  16 ###
  17 #
  18 #
  19 ###
  20 ### Build the objects we have code for in this directory.
  21 ###
  22 ##object mainboard.o
  23 config chip.h
  24 register "fixup_scsi" = "1"
  25 register "fixup_vga" = "1"
  26
  27
  28 ##
  29 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  30 ##
  31 default LB_CKS_RANGE_START=49
  32 default LB_CKS_RANGE_END=122
  33 default LB_CKS_LOC=123
  34
  35 driver mainboard.o
  36 #dir /drvers/adaptec/7902
  37 #dir /drivers/si/3114
  38 #dir /drivers/intel/82551_ipmi
  39 #dir /drivers/ati/ragexl
  40 if HAVE_MP_TABLE object mptable.o end
  41 if HAVE_PIRQ_TABLE object irq_tables.o end
  42 #
  43 #default HARD_RESET_BUS=1
  44 #default HARD_RESET_DEVICE=4
  45 #default HARD_RESET_FUNCTION=0
  46 #
  47 arch i386 end
  48 #
  49 ###
  50 ### Build our 16 bit and 32 bit linuxBIOS entry code
  51 ###
  52 mainboardinit cpu/i386/entry16.inc
  53 mainboardinit cpu/i386/entry32.inc
  54 mainboardinit cpu/i386/bist32.inc
  55 ldscript /cpu/i386/entry16.lds
  56 ldscript /cpu/i386/entry32.lds
  57 #
  58 ###
  59 ### Build our reset vector (This is where linuxBIOS is entered)
  60 ###
  61 if USE_FALLBACK_IMAGE
  62         mainboardinit cpu/i386/reset16.inc
  63         ldscript /cpu/i386/reset16.lds
  64 else
  65         mainboardinit cpu/i386/reset32.inc
  66         ldscript /cpu/i386/reset32.lds
  67 end
  68 #
  69 #### Should this be in the northbridge code?
  70 mainboardinit arch/i386/lib/cpu_reset.inc
  71 #
  72 ###
  73 ### Include an id string (For safe flashing)
  74 ###
  75 mainboardinit arch/i386/lib/id.inc
  76 ldscript /arch/i386/lib/id.lds
  77 #
  78 ####
  79 #### This is the early phase of linuxBIOS startup
  80 #### Things are delicate and we test to see if we should
  81 #### failover to another image.
  82 ####
  83 #option MAX_REBOOT_CNT=2
  84 if USE_FALLBACK_IMAGE
  85   ldscript /arch/i386/lib/failover.lds
  86 end
  87 #
  88 ###
  89 ### Setup our mtrrs
  90 ###
  91 #mainboardinit cpu/p6/earlymtrr.inc
  92 ###
  93 ### Only the bootstrap cpu makes it here.
  94 ### Failover if we need to
  95 ###
  96 #
  97 if USE_FALLBACK_IMAGE
  98   mainboardinit ./failover.inc
  99 end
 100
 101 #
 102 #
 103 ###
 104 ### Setup the serial port
 105 ###
 106 mainboardinit pc80/serial.inc
 107 mainboardinit arch/i386/lib/console.inc
 108 mainboardinit cpu/i386/bist32_fail.inc
 109 #
 110 ####
 111 #### O.k. We aren't just an intermediary anymore!
 112 ####
 113 #
 114 ###
 115 ### When debugging disable the watchdog timer
 116 ###
 117 ##option MAXIMUM_CONSOLE_LOGLEVEL=7
 118 #default MAXIMUM_CONSOLE_LOGLEVEL=7
 119 #
 120 #if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
 121 #
 122 ###
 123 ### Romcc output
 124 ###
 125
 126 makerule ./failover.E
 127         depends "$(MAINBOARD)/failover.c"
 128         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 129 end
 130
 131 makerule ./failover.inc
 132         depends "./romcc ./failover.E"
 133         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 134 end
 135
 136 makerule ./auto.E
 137         depends "$(MAINBOARD)/auto.c option_table.h"
 138         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 139 end
 140 makerule ./auto.inc
 141         depends "./romcc ./auto.E"
 142         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 143 #        action  "./romcc -O2 ./auto.E > auto.inc"
 144 end
 145 mainboardinit cpu/p6/enable_mmx_sse.inc
 146 mainboardinit ./auto.inc
 147 mainboardinit cpu/p6/disable_mmx_sse.inc
 148 #
 149 ###
 150 ### Include the secondary Configuration files
 151 ###
 152
 153 config chip.h
 154
 155 northbridge intel/e7501 "e7501"
 156                 pci 0:2.0
 157                 pci 0:0.0
 158                 pci 0:0.1
 159                 pci 0:6.0
 160         southbridge intel/i82870 "i82870"
 161                 pci 0:1c.0
 162                 pci 0:1d.0
 163                 pci 0:1e.0
 164                 pci 0:1f.0
 165         end
 166 end
 167         southbridge intel/i82801er "i82801er"
 168                 pci 0:1f.0
 169                 pci 0:1d.0 on
 170                 pci 0:1d.1 on
 171                 pci 0:1d.2 on
 172                 pci 0:1d.3 on
 173                 pci 0:1d.7 on
 174                 pci 0:1e.0 on
 175                 pci 0:1f.1 off
 176                 pci 0:1f.2 on
 177                 pci 0:1f.3 on
 178                 pci 0:1f.5 off
 179                 pci 0:1f.6 off
 180 #                pci 1:8.0 off
 181                 superio winbond/w83627hf
 182                         pnp 2e.0 on #  Floppy
 183                                  io 0x60 = 0x3f0
 184                                 irq 0x70 = 6
 185                                 drq 0x74 = 2
 186                         pnp 2e.1 off #  Parallel Port
 187                                  io 0x60 = 0x378
 188                                 irq 0x70 = 7
 189                         pnp 2e.2 on #  Com1
 190                                  io 0x60 = 0x3f8
 191                                 irq 0x70 = 4
 192                         pnp 2e.3 off #  Com2
 193                                  io 0x60 = 0x2f8
 194                                 irq 0x70 = 3
 195                         pnp 2e.5 on #  Keyboard
 196                                  io 0x60 = 0x60
 197                                  io 0x62 = 0x64
 198                                 irq 0x70 = 1
 199                                 irq 0x72 = 12
 200                         pnp 2e.6 off #  CIR
 201                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 202                         pnp 2e.8 off #  GPIO2
 203                         pnp 2e.9 off #  GPIO3
 204                         pnp 2e.a off #  ACPI
 205                         pnp 2e.b on  #  HW Monitor
 206                                  io 0x60 = 0x290
 207                 end
 208         end
 209 #end
 210 dir /pc80
 211 #dir /bioscall
 212 cpu p6 "cpu0"
 213 end
 214
 215 cpu p6 "cpu1"
 216 end
 217
 218 cpu p6 "cpu2"
 219 end
 220
 221 cpu p6 "cpu3"
 222 end