4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_ROM_PAYLOAD
15 uses MAINBOARD_PART_NUMBER
16 uses COREBOOT_EXTRA_VERSION
25 uses ROM_SECTION_OFFSET
26 uses CONFIG_ROM_PAYLOAD_START
27 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
28 uses CONFIG_PRECOMPRESSED_PAYLOAD
44 uses CONFIG_CONSOLE_SERIAL8250
47 uses DEFAULT_CONSOLE_LOGLEVEL
48 uses MAXIMUM_CONSOLE_LOGLEVEL
50 default CONFIG_CONSOLE_SERIAL8250=1
51 ## Select the serial console baud rate
52 default TTYS0_BAUD=115200
53 #default TTYS0_BAUD=57600
54 #default TTYS0_BAUD=38400
55 #default TTYS0_BAUD=19200
56 #default TTYS0_BAUD=9600
57 #default TTYS0_BAUD=4800
58 #default TTYS0_BAUD=2400
59 #default TTYS0_BAUD=1200
61 # Select the serial console base port
62 default TTYS0_BASE=0x2f8
64 # Select the serial protocol
65 # This defaults to 8 data bits, 1 stop bit, and no parity
69 default DEFAULT_CONSOLE_LOGLEVEL=9
70 default MAXIMUM_CONSOLE_LOGLEVEL=9
71 ## ROM_SIZE is the size of boot ROM that this board will use.
72 default ROM_SIZE = 256*1024
79 ## Build code for the fallback boot
81 default HAVE_FALLBACK_BOOT=1
86 default HAVE_MP_TABLE=0
89 ## Build code to reset the motherboard from coreboot
91 default HAVE_HARD_RESET=0
94 ## Build code to export a programmable irq routing table
96 default HAVE_PIRQ_TABLE=1
97 default IRQ_SLOT_COUNT=7
101 ## Build code to export a CMOS option table
103 default HAVE_OPTION_TABLE=1
106 ### coreboot layout values
109 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
110 default ROM_IMAGE_SIZE = 65536
111 default FALLBACK_SIZE = 131072
114 ## Use a small 8K stack
116 default STACK_SIZE=0x2000
119 ## Use a small 16K heap
121 default HEAP_SIZE=0x4000
124 ## Only use the option table in a normal image
126 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
127 default USE_OPTION_TABLE = 0
129 default _RAMBASE = 0x00004000
131 default CONFIG_ROM_PAYLOAD = 1
134 ## The default compiler
136 default CC="$(CROSS_COMPILE)gcc -m32"
143 default CONFIG_ROMFS=0