2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
25 "TECHNEXION", /* OEMID */
26 "TIM-8690", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
61 /* PIC IRQ mapping registers, C00h-C01h */
62 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
63 Field(PRQM, ByteAcc, NoLock, Preserve) {
65 PRQD, 0x00000008, /* Offset: 1h */
67 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
68 PINA, 0x00000008, /* Index 0 */
69 PINB, 0x00000008, /* Index 1 */
70 PINC, 0x00000008, /* Index 2 */
71 PIND, 0x00000008, /* Index 3 */
72 AINT, 0x00000008, /* Index 4 */
73 SINT, 0x00000008, /* Index 5 */
74 , 0x00000008, /* Index 6 */
75 AAUD, 0x00000008, /* Index 7 */
76 AMOD, 0x00000008, /* Index 8 */
77 PINE, 0x00000008, /* Index 9 */
78 PINF, 0x00000008, /* Index A */
79 PING, 0x00000008, /* Index B */
80 PINH, 0x00000008, /* Index C */
83 /* PCI Error control register */
84 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
85 Field(PERC, ByteAcc, NoLock, Preserve) {
92 /* Client Management index/data registers */
93 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
94 Field(CMT, ByteAcc, NoLock, Preserve) {
96 /* Client Management Data register */
104 /* GPM Port register */
105 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
106 Field(GPT, ByteAcc, NoLock, Preserve) {
117 /* Flash ROM program enable register */
118 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
119 Field(FRE, ByteAcc, NoLock, Preserve) {
124 /* PM2 index/data registers */
125 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
126 Field(PM2R, ByteAcc, NoLock, Preserve) {
131 /* Power Management I/O registers */
132 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
133 Field(PIOR, ByteAcc, NoLock, Preserve) {
137 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
138 Offset(0x00), /* MiscControl */
142 Offset(0x01), /* MiscStatus */
146 Offset(0x04), /* SmiWakeUpEventEnable3 */
149 Offset(0x07), /* SmiWakeUpEventStatus3 */
152 Offset(0x10), /* AcpiEnable */
155 Offset(0x1C), /* ProgramIoEnable */
162 Offset(0x1D), /* IOMonitorStatus */
169 Offset(0x20), /* AcpiPmEvtBlk */
171 Offset(0x36), /* GEvtLevelConfig */
175 Offset(0x37), /* GPMLevelConfig0 */
182 Offset(0x38), /* GPMLevelConfig1 */
189 Offset(0x3B), /* PMEStatus1 */
198 Offset(0x55), /* SoftPciRst */
206 /* Offset(0x61), */ /* Options_1 */
210 Offset(0x65), /* UsbPMControl */
213 Offset(0x68), /* MiscEnable68 */
217 Offset(0x92), /* GEVENTIN */
220 Offset(0x96), /* GPM98IN */
223 Offset(0x9A), /* EnhanceControl */
226 Offset(0xA8), /* PIO7654Enable */
231 Offset(0xA9), /* PIO7654Status */
239 * First word is PM1_Status, Second word is PM1_Enable
241 OperationRegion(P1EB, SystemIO, APEB, 0x04)
242 Field(P1EB, ByteAcc, NoLock, Preserve) {
268 /* PCIe Configuration Space for 16 busses */
269 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
270 Field(PCFG, ByteAcc, NoLock, Preserve) {
271 /* Byte offsets are computed using the following technique:
272 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
273 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
275 Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
277 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
288 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
291 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
293 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
295 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
297 P92E, 1, /* Port92 decode enable */
300 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
301 Field(SB5, AnyAcc, NoLock, Preserve)
304 Offset(0x120), /* Port 0 Task file status */
310 Offset(0x128), /* Port 0 Serial ATA status */
314 Offset(0x12C), /* Port 0 Serial ATA control */
316 Offset(0x130), /* Port 0 Serial ATA error */
321 offset(0x1A0), /* Port 1 Task file status */
327 Offset(0x1A8), /* Port 1 Serial ATA status */
331 Offset(0x1AC), /* Port 1 Serial ATA control */
333 Offset(0x1B0), /* Port 1 Serial ATA error */
338 Offset(0x220), /* Port 2 Task file status */
344 Offset(0x228), /* Port 2 Serial ATA status */
348 Offset(0x22C), /* Port 2 Serial ATA control */
350 Offset(0x230), /* Port 2 Serial ATA error */
355 Offset(0x2A0), /* Port 3 Task file status */
361 Offset(0x2A8), /* Port 3 Serial ATA status */
365 Offset(0x2AC), /* Port 3 Serial ATA control */
367 Offset(0x2B0), /* Port 3 Serial ATA error */
373 #include "acpi/routing.asl"
379 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
381 if(CondRefOf(\_OSI,Local1))
383 Store(1, OSTP) /* Assume some form of XP */
384 if (\_OSI("Windows 2006")) /* Vista */
389 If(WCMP(\_OS,"Linux")) {
390 Store(3, OSTP) /* Linux */
392 Store(4, OSTP) /* Gotta be WinCE */
398 Method(_PIC, 0x01, NotSerialized)
407 Method(CIRQ, 0x00, NotSerialized)
419 Name(IRQB, ResourceTemplate(){
420 IRQ(Level,ActiveLow,Shared){15}
423 Name(IRQP, ResourceTemplate(){
424 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
427 Name(PITF, ResourceTemplate(){
428 IRQ(Level,ActiveLow,Exclusive){9}
432 Name(_HID, EISAID("PNP0C0F"))
437 Return(0x0B) /* sata is invisible */
439 Return(0x09) /* sata is disabled */
441 } /* End Method(_SB.INTA._STA) */
444 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
446 } /* End Method(_SB.INTA._DIS) */
449 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
451 } /* Method(_SB.INTA._PRS) */
454 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
455 CreateWordField(IRQB, 0x1, IRQN)
456 ShiftLeft(1, PINA, IRQN)
458 } /* Method(_SB.INTA._CRS) */
461 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
462 CreateWordField(ARG0, 1, IRQM)
464 /* Use lowest available IRQ */
465 FindSetRightBit(IRQM, Local0)
470 } /* End Method(_SB.INTA._SRS) */
471 } /* End Device(INTA) */
474 Name(_HID, EISAID("PNP0C0F"))
479 Return(0x0B) /* sata is invisible */
481 Return(0x09) /* sata is disabled */
483 } /* End Method(_SB.INTB._STA) */
486 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
488 } /* End Method(_SB.INTB._DIS) */
491 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
493 } /* Method(_SB.INTB._PRS) */
496 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
497 CreateWordField(IRQB, 0x1, IRQN)
498 ShiftLeft(1, PINB, IRQN)
500 } /* Method(_SB.INTB._CRS) */
503 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
504 CreateWordField(ARG0, 1, IRQM)
506 /* Use lowest available IRQ */
507 FindSetRightBit(IRQM, Local0)
512 } /* End Method(_SB.INTB._SRS) */
513 } /* End Device(INTB) */
516 Name(_HID, EISAID("PNP0C0F"))
521 Return(0x0B) /* sata is invisible */
523 Return(0x09) /* sata is disabled */
525 } /* End Method(_SB.INTC._STA) */
528 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
530 } /* End Method(_SB.INTC._DIS) */
533 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
535 } /* Method(_SB.INTC._PRS) */
538 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
539 CreateWordField(IRQB, 0x1, IRQN)
540 ShiftLeft(1, PINC, IRQN)
542 } /* Method(_SB.INTC._CRS) */
545 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
546 CreateWordField(ARG0, 1, IRQM)
548 /* Use lowest available IRQ */
549 FindSetRightBit(IRQM, Local0)
554 } /* End Method(_SB.INTC._SRS) */
555 } /* End Device(INTC) */
558 Name(_HID, EISAID("PNP0C0F"))
563 Return(0x0B) /* sata is invisible */
565 Return(0x09) /* sata is disabled */
567 } /* End Method(_SB.INTD._STA) */
570 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
572 } /* End Method(_SB.INTD._DIS) */
575 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
577 } /* Method(_SB.INTD._PRS) */
580 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
581 CreateWordField(IRQB, 0x1, IRQN)
582 ShiftLeft(1, PIND, IRQN)
584 } /* Method(_SB.INTD._CRS) */
587 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
588 CreateWordField(ARG0, 1, IRQM)
590 /* Use lowest available IRQ */
591 FindSetRightBit(IRQM, Local0)
596 } /* End Method(_SB.INTD._SRS) */
597 } /* End Device(INTD) */
600 Name(_HID, EISAID("PNP0C0F"))
605 Return(0x0B) /* sata is invisible */
607 Return(0x09) /* sata is disabled */
609 } /* End Method(_SB.INTE._STA) */
612 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
614 } /* End Method(_SB.INTE._DIS) */
617 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
619 } /* Method(_SB.INTE._PRS) */
622 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
623 CreateWordField(IRQB, 0x1, IRQN)
624 ShiftLeft(1, PINE, IRQN)
626 } /* Method(_SB.INTE._CRS) */
629 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
630 CreateWordField(ARG0, 1, IRQM)
632 /* Use lowest available IRQ */
633 FindSetRightBit(IRQM, Local0)
638 } /* End Method(_SB.INTE._SRS) */
639 } /* End Device(INTE) */
642 Name(_HID, EISAID("PNP0C0F"))
647 Return(0x0B) /* sata is invisible */
649 Return(0x09) /* sata is disabled */
651 } /* End Method(_SB.INTF._STA) */
654 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
656 } /* End Method(_SB.INTF._DIS) */
659 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
661 } /* Method(_SB.INTF._PRS) */
664 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
665 CreateWordField(IRQB, 0x1, IRQN)
666 ShiftLeft(1, PINF, IRQN)
668 } /* Method(_SB.INTF._CRS) */
671 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
672 CreateWordField(ARG0, 1, IRQM)
674 /* Use lowest available IRQ */
675 FindSetRightBit(IRQM, Local0)
680 } /* End Method(_SB.INTF._SRS) */
681 } /* End Device(INTF) */
684 Name(_HID, EISAID("PNP0C0F"))
689 Return(0x0B) /* sata is invisible */
691 Return(0x09) /* sata is disabled */
693 } /* End Method(_SB.INTG._STA) */
696 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
698 } /* End Method(_SB.INTG._DIS) */
701 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
703 } /* Method(_SB.INTG._CRS) */
706 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
707 CreateWordField(IRQB, 0x1, IRQN)
708 ShiftLeft(1, PING, IRQN)
710 } /* Method(_SB.INTG._CRS) */
713 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
714 CreateWordField(ARG0, 1, IRQM)
716 /* Use lowest available IRQ */
717 FindSetRightBit(IRQM, Local0)
722 } /* End Method(_SB.INTG._SRS) */
723 } /* End Device(INTG) */
726 Name(_HID, EISAID("PNP0C0F"))
731 Return(0x0B) /* sata is invisible */
733 Return(0x09) /* sata is disabled */
735 } /* End Method(_SB.INTH._STA) */
738 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
740 } /* End Method(_SB.INTH._DIS) */
743 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
745 } /* Method(_SB.INTH._CRS) */
748 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
749 CreateWordField(IRQB, 0x1, IRQN)
750 ShiftLeft(1, PINH, IRQN)
752 } /* Method(_SB.INTH._CRS) */
755 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
756 CreateWordField(ARG0, 1, IRQM)
758 /* Use lowest available IRQ */
759 FindSetRightBit(IRQM, Local0)
764 } /* End Method(_SB.INTH._SRS) */
765 } /* End Device(INTH) */
767 } /* End Scope(_SB) */
770 /* Supported sleep states: */
771 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
773 If (LAnd(SSFG, 0x01)) {
774 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
776 If (LAnd(SSFG, 0x02)) {
777 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
779 If (LAnd(SSFG, 0x04)) {
780 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
782 If (LAnd(SSFG, 0x08)) {
783 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
786 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
788 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
789 Name(CSMS, 0) /* Current System State */
791 /* Wake status package */
792 Name(WKST,Package(){Zero, Zero})
795 * \_PTS - Prepare to Sleep method
798 * Arg0=The value of the sleeping state S1=1, S2=2, etc
803 * The _PTS control method is executed at the beginning of the sleep process
804 * for S1-S5. The sleeping value is passed to the _PTS control method. This
805 * control method may be executed a relatively long time before entering the
806 * sleep state and the OS may abort the operation without notification to
807 * the ACPI driver. This method cannot modify the configuration or power
808 * state of any device in the system.
811 /* DBGO("\\_PTS\n") */
812 /* DBGO("From S0 to S") */
816 /* Don't allow PCIRST# to reset USB */
821 /* Clear sleep SMI status flag and enable sleep SMI trap. */
825 /* On older chips, clear PciExpWakeDisEn */
826 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
831 /* Clear wake status structure. */
832 Store(0, Index(WKST,0))
833 Store(0, Index(WKST,1))
834 \_SB.PCI0.SIOS (Arg0)
835 } /* End Method(\_PTS) */
838 * The following method results in a "not a valid reserved NameSeg"
839 * warning so I have commented it out for the duration. It isn't
840 * used, so it could be removed.
843 * \_GTS OEM Going To Sleep method
846 * Arg0=The value of the sleeping state S1=1, S2=2
853 * DBGO("From S0 to S")
860 * \_BFS OEM Back From Sleep method
863 * Arg0=The value of the sleeping state S1=1, S2=2
869 /* DBGO("\\_BFS\n") */
872 /* DBGO(" to S0\n") */
876 * \_WAK System Wake method
879 * Arg0=The value of the sleeping state S1=1, S2=2
882 * Return package of 2 DWords
884 * 0x00000000 wake succeeded
885 * 0x00000001 Wake was signaled but failed due to lack of power
886 * 0x00000002 Wake was signaled but failed due to thermal condition
887 * Dword 2 - Power Supply state
888 * if non-zero the effective S-state the power supply entered
891 /* DBGO("\\_WAK\n") */
894 /* DBGO(" to S0\n") */
899 /* Restore PCIRST# so it resets USB */
904 /* Arbitrarily clear PciExpWakeStatus */
907 /* if(DeRefOf(Index(WKST,0))) {
908 * Store(0, Index(WKST,1))
910 * Store(Arg0, Index(WKST,1))
913 \_SB.PCI0.SIOW (Arg0)
915 } /* End Method(\_WAK) */
917 Scope(\_GPE) { /* Start Scope GPE */
918 /* General event 0 */
920 * DBGO("\\_GPE\\_L00\n")
924 /* General event 1 */
926 * DBGO("\\_GPE\\_L00\n")
930 /* General event 2 */
932 * DBGO("\\_GPE\\_L00\n")
936 /* General event 3 */
938 /* DBGO("\\_GPE\\_L00\n") */
939 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
942 /* General event 4 */
944 * DBGO("\\_GPE\\_L00\n")
948 /* General event 5 */
950 * DBGO("\\_GPE\\_L00\n")
954 /* General event 6 - Used for GPM6, moved to USB.asl */
956 * DBGO("\\_GPE\\_L00\n")
960 /* General event 7 - Used for GPM7, moved to USB.asl */
962 * DBGO("\\_GPE\\_L07\n")
966 /* Legacy PM event */
968 /* DBGO("\\_GPE\\_L08\n") */
971 /* Temp warning (TWarn) event */
973 /* DBGO("\\_GPE\\_L09\n") */
974 Notify (\_TZ.TZ00, 0x80)
979 * DBGO("\\_GPE\\_L0A\n")
983 /* USB controller PME# */
985 /* DBGO("\\_GPE\\_L0B\n") */
986 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
987 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
988 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
989 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
990 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
991 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
992 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
995 /* AC97 controller PME# */
997 * DBGO("\\_GPE\\_L0C\n")
1001 /* OtherTherm PME# */
1003 * DBGO("\\_GPE\\_L0D\n")
1007 /* GPM9 SCI event - Moved to USB.asl */
1009 * DBGO("\\_GPE\\_L0E\n")
1013 /* PCIe HotPlug event */
1015 * DBGO("\\_GPE\\_L0F\n")
1019 /* ExtEvent0 SCI event */
1021 /* DBGO("\\_GPE\\_L10\n") */
1025 /* ExtEvent1 SCI event */
1027 /* DBGO("\\_GPE\\_L11\n") */
1030 /* PCIe PME# event */
1032 * DBGO("\\_GPE\\_L12\n")
1036 /* GPM0 SCI event - Moved to USB.asl */
1038 * DBGO("\\_GPE\\_L13\n")
1042 /* GPM1 SCI event - Moved to USB.asl */
1044 * DBGO("\\_GPE\\_L14\n")
1048 /* GPM2 SCI event - Moved to USB.asl */
1050 * DBGO("\\_GPE\\_L15\n")
1054 /* GPM3 SCI event - Moved to USB.asl */
1056 * DBGO("\\_GPE\\_L16\n")
1060 /* GPM8 SCI event - Moved to USB.asl */
1062 * DBGO("\\_GPE\\_L17\n")
1066 /* GPIO0 or GEvent8 event */
1068 /* DBGO("\\_GPE\\_L18\n") */
1069 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1070 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1071 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1072 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1073 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1074 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1077 /* GPM4 SCI event - Moved to USB.asl */
1079 * DBGO("\\_GPE\\_L19\n")
1083 /* GPM5 SCI event - Moved to USB.asl */
1085 * DBGO("\\_GPE\\_L1A\n")
1089 /* Azalia SCI event */
1091 /* DBGO("\\_GPE\\_L1B\n") */
1092 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1093 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1096 /* GPM6 SCI event - Reassigned to _L06 */
1098 * DBGO("\\_GPE\\_L1C\n")
1102 /* GPM7 SCI event - Reassigned to _L07 */
1104 * DBGO("\\_GPE\\_L1D\n")
1108 /* GPIO2 or GPIO66 SCI event */
1110 * DBGO("\\_GPE\\_L1E\n")
1114 /* SATA SCI event - Moved to sata.asl */
1116 * DBGO("\\_GPE\\_L1F\n")
1120 } /* End Scope GPE */
1122 #include "acpi/usb.asl"
1125 Scope(\_SB) { /* Start \_SB scope */
1126 #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1129 /* Note: Only need HID on Primary Bus */
1133 Name(_HID, EISAID("PNP0A03"))
1134 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1135 Method(_BBN, 0) { /* Bus number = 0 */
1139 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1140 Return(0x0B) /* Status is visible */
1144 If(PMOD){ Return(APR0) } /* APIC mode */
1145 Return (PR0) /* PIC Mode */
1148 /* Describe the Northbridge devices */
1150 Name(_ADR, 0x00000000)
1153 /* The internal GFX bridge */
1155 Name(_ADR, 0x00010000)
1156 Name(_PRW, Package() {0x18, 4})
1162 /* The external GFX bridge */
1164 Name(_ADR, 0x00020000)
1165 Name(_PRW, Package() {0x18, 4})
1167 If(PMOD){ Return(APS2) } /* APIC mode */
1168 Return (PS2) /* PIC Mode */
1172 /* Dev3 is also an external GFX bridge, not used in Herring */
1175 Name(_ADR, 0x00040000)
1176 Name(_PRW, Package() {0x18, 4})
1178 If(PMOD){ Return(APS4) } /* APIC mode */
1179 Return (PS4) /* PIC Mode */
1184 Name(_ADR, 0x00050000)
1185 Name(_PRW, Package() {0x18, 4})
1187 If(PMOD){ Return(APS5) } /* APIC mode */
1188 Return (PS5) /* PIC Mode */
1193 Name(_ADR, 0x00060000)
1194 Name(_PRW, Package() {0x18, 4})
1196 If(PMOD){ Return(APS6) } /* APIC mode */
1197 Return (PS6) /* PIC Mode */
1201 /* The onboard EtherNet chip */
1203 Name(_ADR, 0x00070000)
1204 Name(_PRW, Package() {0x18, 4})
1206 If(PMOD){ Return(APS7) } /* APIC mode */
1207 Return (PS7) /* PIC Mode */
1212 /* PCI slot 1, 2, 3 */
1214 Name(_ADR, 0x00140004)
1215 Name(_PRW, Package() {0x18, 4})
1222 /* Describe the Southbridge devices */
1224 Name(_ADR, 0x00120000)
1225 #include "acpi/sata.asl"
1229 Name(_ADR, 0x00130000)
1230 Name(_PRW, Package() {0x0B, 3})
1234 Name(_ADR, 0x00130001)
1235 Name(_PRW, Package() {0x0B, 3})
1239 Name(_ADR, 0x00130002)
1240 Name(_PRW, Package() {0x0B, 3})
1244 Name(_ADR, 0x00130003)
1245 Name(_PRW, Package() {0x0B, 3})
1249 Name(_ADR, 0x00130004)
1250 Name(_PRW, Package() {0x0B, 3})
1254 Name(_ADR, 0x00130005)
1255 Name(_PRW, Package() {0x0B, 3})
1259 Name(_ADR, 0x00140000)
1262 /* Primary (and only) IDE channel */
1264 Name(_ADR, 0x00140001)
1265 #include "acpi/ide.asl"
1269 Name(_ADR, 0x00140002)
1270 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1271 Field(AZPD, AnyAcc, NoLock, Preserve) {
1295 If(LEqual(OSTP,3)){ /* If we are running Linux */
1304 Name(_ADR, 0x00140003)
1306 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1307 } */ /* End Method(_SB.SBRDG._INI) */
1309 /* Real Time Clock Device */
1311 Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
1312 Name(_CRS, ResourceTemplate() {
1314 IO(Decode16,0x0070, 0x0070, 0, 2)
1315 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1317 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1319 Device(TMR) { /* Timer */
1320 Name(_HID,EISAID("PNP0100")) /* System Timer */
1321 Name(_CRS, ResourceTemplate() {
1323 IO(Decode16, 0x0040, 0x0040, 0, 4)
1324 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1326 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1328 Device(SPKR) { /* Speaker */
1329 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1330 Name(_CRS, ResourceTemplate() {
1331 IO(Decode16, 0x0061, 0x0061, 0, 1)
1333 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1336 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1337 Name(_CRS, ResourceTemplate() {
1339 IO(Decode16,0x0020, 0x0020, 0, 2)
1340 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1341 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1342 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1344 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1346 Device(MAD) { /* 8257 DMA */
1347 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1348 Name(_CRS, ResourceTemplate() {
1349 DMA(Compatibility,BusMaster,Transfer8){4}
1350 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1351 IO(Decode16, 0x0081, 0x0081, 0x10, 0x03)
1352 IO(Decode16, 0x0087, 0x0087, 0x10, 0x01)
1353 IO(Decode16, 0x0089, 0x0089, 0x10, 0x03)
1354 IO(Decode16, 0x008F, 0x008F, 0x10, 0x01)
1355 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1356 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1357 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1360 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1361 Name(_CRS, ResourceTemplate() {
1362 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1365 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1368 Name(_HID,EISAID("PNP0103"))
1369 Name(CRS,ResourceTemplate() {
1370 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1373 Return(0x0F) /* sata is visible */
1376 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1380 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1384 Name(_ADR, 0x00140004)
1385 } /* end HostPciBr */
1388 Name(_ADR, 0x00140005)
1389 } /* end Ac97audio */
1392 Name(_ADR, 0x00140006)
1393 } /* end Ac97modem */
1395 /* ITE IT8712F Support */
1396 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1397 Field (IOID, ByteAcc, NoLock, Preserve)
1399 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1402 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1405 LDN, 8, /* Logical Device Number */
1407 CID1, 8, /* Chip ID Byte 1, 0x87 */
1408 CID2, 8, /* Chip ID Byte 2, 0x12 */
1410 ACTR, 8, /* Function activate */
1412 APC0, 8, /* APC/PME Event Enable Register */
1413 APC1, 8, /* APC/PME Status Register */
1414 APC2, 8, /* APC/PME Control Register 1 */
1415 APC3, 8, /* Environment Controller Special Configuration Register */
1416 APC4, 8 /* APC/PME Control Register 2 */
1419 /* Enter the IT8712F MB PnP Mode */
1425 Store(0x55, SIOI) /* IT8712F magic number */
1427 /* Exit the IT8712F MB PnP Mode */
1435 * Keyboard PME is routed to SB600 Gevent3. We can wake
1436 * up the system by pressing the key.
1440 /* We only enable KBD PME for S5. */
1441 If (LLess (Arg0, 0x05))
1444 /* DBGO("IT8712F\n") */
1447 Store (One, ACTR) /* Enable EC */
1451 */ /* falling edge. which mode? Not sure. */
1454 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1456 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1465 Store (Zero, APC0) /* disable keyboard PME */
1467 Store (0xFF, APC1) /* clear keyboard PME status */
1471 Name(CRES, ResourceTemplate() {
1472 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1474 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1475 0x0000, /* address granularity */
1476 0x0000, /* range minimum */
1477 0x0CF7, /* range maximum */
1478 0x0000, /* translation */
1482 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1483 0x0000, /* address granularity */
1484 0x0D00, /* range minimum */
1485 0xFFFF, /* range maximum */
1486 0x0000, /* translation */
1490 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1491 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1492 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1493 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1495 /* DRAM Memory from 1MB to TopMem */
1496 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1498 /* BIOS space just below 4GB */
1500 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1501 0x00, /* Granularity */
1502 0x00000000, /* Min */
1503 0x00000000, /* Max */
1504 0x00000000, /* Translation */
1505 0x00000000, /* Max-Min, RLEN */
1510 /* DRAM memory from 4GB to TopMem2 */
1511 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1512 0xFFFFFFFF, /* Granularity */
1513 0x00000000, /* Min */
1514 0x00000000, /* Max */
1515 0x00000000, /* Translation */
1516 0x00000000, /* Max-Min, RLEN */
1521 /* BIOS space just below 16EB */
1522 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1523 0xFFFFFFFF, /* Granularity */
1524 0x00000000, /* Min */
1525 0x00000000, /* Max */
1526 0x00000000, /* Translation */
1527 0x00000000, /* Max-Min, RLEN */
1532 }) /* End Name(_SB.PCI0.CRES) */
1535 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1537 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1538 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1539 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1540 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1541 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1542 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1544 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1545 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1546 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1547 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1549 If(LGreater(LOMH, 0xC0000)){
1550 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1551 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1554 /* Set size of memory from 1MB to TopMem */
1555 Subtract(TOM1, 0x100000, DMLL)
1558 * If(LNotEqual(TOM2, 0x00000000)){
1559 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1560 * Subtract(TOM2, 0x100000000, DMHL)
1564 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1565 If(LEqual(TOM2, 0x00000000)){
1566 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1569 Else { /* Otherwise, put the BIOS just below 16EB */
1570 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1574 Return(CRES) /* note to change the Name buffer */
1575 } /* end of Method(_SB.PCI0._CRS) */
1579 * FIRST METHOD CALLED UPON BOOT
1581 * 1. If debugging, print current OS and ACPI interpreter.
1582 * 2. Get PCI Interrupt routing from ACPI VSM, this
1583 * value is based on user choice in BIOS setup.
1586 /* DBGO("\\_SB\\_INI\n") */
1587 /* DBGO(" DSDT.ASL code from ") */
1588 /* DBGO(__DATE__) */
1590 /* DBGO(__TIME__) */
1591 /* DBGO("\n Sleep states supported: ") */
1593 /* DBGO(" \\_OS=") */
1595 /* DBGO("\n \\_REV=") */
1599 /* Determine the OS we're running on */
1602 /* On older chips, clear PciExpWakeDisEn */
1603 /*if (LLessEqual(\SBRI, 0x13)) {
1607 } /* End Method(_SB._INI) */
1608 } /* End Device(PCI0) */
1610 Device(PWRB) { /* Start Power button device */
1611 Name(_HID, EISAID("PNP0C0C"))
1613 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1614 Name(_STA, 0x0B) /* sata is invisible */
1616 } /* End \_SB scope */
1620 /* DBGO("\\_SI\\_SST\n") */
1621 /* DBGO(" New Indicator state: ") */
1625 } /* End Scope SI */
1628 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1629 Field (SMB0, ByteAcc, NoLock, Preserve) {
1630 HSTS, 8, /* SMBUS status */
1631 SSTS, 8, /* SMBUS slave status */
1632 HCNT, 8, /* SMBUS control */
1633 HCMD, 8, /* SMBUS host cmd */
1634 HADD, 8, /* SMBUS address */
1635 DAT0, 8, /* SMBUS data0 */
1636 DAT1, 8, /* SMBUS data1 */
1637 BLKD, 8, /* SMBUS block data */
1638 SCNT, 8, /* SMBUS slave control */
1639 SCMD, 8, /* SMBUS shaow cmd */
1640 SEVT, 8, /* SMBUS slave event */
1641 SDAT, 8 /* SMBUS slave data */
1644 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1646 Store (0xFA, Local0)
1647 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1655 Method (SWTC, 1, NotSerialized) {
1656 Store (Arg0, Local0)
1657 Store (0x07, Local2)
1659 While (LEqual (Local1, One)) {
1660 Store (And (HSTS, 0x1E), Local3)
1661 If (LNotEqual (Local3, Zero)) { /* read sucess */
1662 If (LEqual (Local3, 0x02)) {
1663 Store (Zero, Local2)
1666 Store (Zero, Local1)
1669 If (LLess (Local0, 0x0A)) { /* read failure */
1670 Store (0x10, Local2)
1671 Store (Zero, Local1)
1674 Sleep (0x0A) /* 10 ms, try again */
1675 Subtract (Local0, 0x0A, Local0)
1683 Method (SMBR, 3, NotSerialized) {
1684 Store (0x07, Local0)
1685 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1686 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1687 If (LEqual (Local0, Zero)) {
1693 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1695 If (LEqual (Arg0, 0x07)) {
1696 Store (0x48, HCNT) /* read byte */
1699 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1700 If (LEqual (Local1, Zero)) {
1701 If (LEqual (Arg0, 0x07)) {
1702 Store (DAT0, Local0)
1706 Store (Local1, Local0)
1712 /* DBGO("the value of SMBusData0 register ") */
1728 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1729 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1730 Return(Add(0, 2730))
1732 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1733 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1734 Return(Package() {\_TZ.TZ00.FAN0})
1737 Name(_HID, EISAID("PNP0C0B"))
1738 Name(_PR0, Package() {PFN0})
1741 PowerResource(PFN0,0,0) {
1747 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1750 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1754 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1755 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1756 Return (Add (THOT, KELV))
1758 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1759 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1760 Return (Add (TCRT, KELV))
1762 Method(_TMP,0) { /* return current temp of this zone */
1763 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1764 If (LGreater (Local0, 0x10)) {
1765 Store (Local0, Local1)
1768 Add (Local0, THOT, Local0)
1769 Return (Add (400, KELV))
1772 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1773 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1774 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1775 If (LGreater (Local0, 0x10)) {
1776 If (LGreater (Local0, Local1)) {
1777 Store (Local0, Local1)
1780 Multiply (Local1, 10, Local1)
1781 Return (Add (Local1, KELV))
1784 Add (Local0, THOT, Local0)
1785 Return (Add (400 , KELV))
1791 /* End of ASL file */