src/mainboard/supermicro/x6dhe_g/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "pc80/udelay_io.c"
  11 #include "lib/delay.c"
  12 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
  13 #include "northbridge/intel/e7520/raminit.h"
  14 #include "superio/winbond/w83627hf/w83627hf.h"
  15 #include "cpu/x86/lapic/boot_cpu.c"
  16 #include "cpu/x86/mtrr/earlymtrr.c"
  17 #include "debug.c"
  18 #include "watchdog.c"
  19 #include "reset.c"
  20 #include "x6dhe_g_fixups.c"
  21 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  22 #include "northbridge/intel/e7520/memory_initialized.c"
  23 #include "cpu/x86/bist.h"
  24
  25 #define SIO_GPIO_BASE 0x680
  26 #define SIO_XBUS_BASE 0x4880
  27
  28 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  30
  31 #define DEVPRES_CONFIG  ( \
  32         DEVPRES_D1F0 | \
  33         DEVPRES_D2F0 | \
  34         DEVPRES_D3F0 | \
  35         DEVPRES_D4F0 | \
  36         DEVPRES_D6F0 | \
  37         0 )
  38 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  39
  40 #define RECVENA_CONFIG  0x0808090a
  41 #define RECVENB_CONFIG  0x0808090a
  42
  43 static inline int spd_read_byte(unsigned device, unsigned address)
  44 {
  45         return smbus_read_byte(device, address);
  46 }
  47
  48 #include "northbridge/intel/e7520/raminit.c"
  49 #include "lib/generic_sdram.c"
  50 #include "arch/i386/lib/stages.c"
  51
  52 static void main(unsigned long bist)
  53 {
  54         /*
  55          *
  56          *
  57          */
  58         static const struct mem_controller mch[] = {
  59                 {
  60                         .node_id = 0,
  61                         /*
  62                         .f0 = PCI_DEV(0, 0x00, 0),
  63                         .f1 = PCI_DEV(0, 0x00, 1),
  64                         .f2 = PCI_DEV(0, 0x00, 2),
  65                         .f3 = PCI_DEV(0, 0x00, 3),
  66                         */
  67                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
  68                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
  69                 }
  70         };
  71
  72         if (bist == 0) {
  73                 /* Skip this if there was a built in self test failure */
  74                 early_mtrr_init();
  75                 if (memory_initialized()) {
  76                         skip_romstage();
  77                 }
  78         }
  79         /* Setup the console */
  80         outb(0x87,0x2e);
  81         outb(0x87,0x2e);
  82         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  83         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  84         uart_init();
  85         console_init();
  86
  87         /* Halt if there was a built in self test failure */
  88 //      report_bist_failure(bist);
  89
  90         /* MOVE ME TO A BETTER LOCATION !!! */
  91         /* config LPC decode for flash memory access */
  92         device_t dev;
  93         dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
  94         if (dev == PCI_DEV_INVALID) {
  95                 die("Missing esb6300?");
  96         }
  97         pci_write_config32(dev, 0xe8, 0x00000000);
  98         pci_write_config8(dev, 0xf0, 0x00);
  99
 100 #if 0
 101         display_cpuid_update_microcode();
 102 #endif
 103 #if 0
 104         print_pci_devices();
 105 #endif
 106 #if 1
 107         enable_smbus();
 108 #endif
 109 #if 0
 110 //      dump_spd_registers(&cpu[0]);
 111         int i;
 112         for(i = 0; i < 1; i++) {
 113                 dump_spd_registers();
 114         }
 115 #endif
 116         disable_watchdogs();
 117 //      dump_ipmi_registers();
 118 //      mainboard_set_e7520_leds();
 119         sdram_initialize(ARRAY_SIZE(mch), mch);
 120 #if 0
 121         dump_pci_devices();
 122 #endif
 123 #if 0
 124         dump_pci_device(PCI_DEV(0, 0x00, 0));
 125         dump_bar14(PCI_DEV(0, 0x00, 0));
 126 #endif
 127
 128 #if 0 // temporarily disabled
 129         /* Check the first 1M */
 130 //      ram_check(0x00000000, 0x000100000);
 131 //      ram_check(0x00000000, 0x000a0000);
 132         ram_check(0x00100000, 0x01000000);
 133         /* check the first 1M in the 3rd Gig */
 134         ram_check(0x30100000, 0x31000000);
 135 #endif
 136 #if 0
 137         ram_check(0x00000000, 0x02000000);
 138 #endif
 139
 140 #if 0
 141         while(1) {
 142                 hlt();
 143         }
 144 #endif
 145 }
 146