src/mainboard/supermicro/h8qme_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define ASSEMBLY 1
  23 #define __PRE_RAM__
  24
  25 #define RAMINIT_SYSINFO 1
  26
  27 #define FAM10_SCAN_PCI_BUS 0
  28 #define FAM10_ALLOCATE_IO_RANGE 1
  29
  30 #define QRANK_DIMM_SUPPORT 1
  31
  32 #if CONFIG_LOGICAL_CPUS==1
  33 #define SET_NB_CFG_54 1
  34 #endif
  35
  36 #define FAM10_SET_FIDVID 1
  37 #define FAM10_SET_FIDVID_CORE_RANGE 0
  38
  39 #include <stdint.h>
  40 #include <string.h>
  41 #include <device/pci_def.h>
  42 #include <device/pci_ids.h>
  43 #include <arch/io.h>
  44 #include <device/pnp_def.h>
  45 #include <arch/romcc_io.h>
  46 #include <cpu/x86/lapic.h>
  47 #include "option_table.h"
  48 #include "pc80/mc146818rtc_early.c"
  49
  50 // for enable the FAN
  51 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  52
  53 static void post_code(u8 value) {
  54         outb(value, 0x80);
  55 }
  56
  57 #include "pc80/serial.c"
  58 #include "arch/i386/lib/console.c"
  59 #include "lib/ramtest.c"
  60
  61 #include <cpu/amd/model_10xxx_rev.h>
  62
  63 //#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  64 #include "northbridge/amd/amdfam10/raminit.h"
  65 #include "northbridge/amd/amdfam10/amdfam10.h"
  66
  67 #include "cpu/x86/lapic/boot_cpu.c"
  68 #include "northbridge/amd/amdfam10/reset_test.c"
  69 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  70 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  71
  72 #include "cpu/x86/bist.h"
  73
  74 #include "northbridge/amd/amdfam10/debug.c"
  75
  76 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  77
  78
  79 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  80
  81 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  82
  83 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  84
  85 static void memreset_setup(void)
  86 {
  87 }
  88
  89 static void memreset(int controllers, const struct mem_controller *ctrl)
  90 {
  91 }
  92
  93 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  94 {
  95 #define SMBUS_SWITCH1 0x70
  96 #define SMBUS_SWITCH2 0x72
  97         smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
  98         smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
  99 }
 100
 101 static inline int spd_read_byte(unsigned device, unsigned address)
 102 {
 103         return smbus_read_byte(device, address);
 104 }
 105
 106 #include "northbridge/amd/amdfam10/amdfam10.h"
 107 #include "northbridge/amd/amdht/ht_wrapper.c"
 108
 109 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 110 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 111 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 112
 113 #include "resourcemap.c"
 114
 115 #include "cpu/amd/quadcore/quadcore.c"
 116
 117 #define MCP55_NUM 1
 118 #define MCP55_USE_NIC 0
 119 #define MCP55_USE_AZA 0
 120
 121 #define MCP55_PCI_E_X_0 4
 122
 123 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 124 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 125
 126 #include "cpu/amd/car/copy_and_run.c"
 127
 128 #include "cpu/amd/car/post_cache_as_ram.c"
 129
 130 #include "cpu/amd/model_10xxx/init_cpus.c"
 131
 132 #include "cpu/amd/model_10xxx/fidvid.c"
 133
 134 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 135 #include "northbridge/amd/amdfam10/early_ht.c"
 136
 137
 138 static void sio_setup(void)
 139 {
 140
 141         unsigned value;
 142         uint32_t dword;
 143         uint8_t byte;
 144         enable_smbus();
 145 //      smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
 146         smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
 147
 148         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 149         byte |= 0x20;
 150         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 151
 152         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 153         dword |= (1<<0);
 154         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 155
 156         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 157         dword |= (1<<16);
 158         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 159
 160 }
 161
 162 #include "spd_addr.h"
 163 #include "cpu/amd/microcode/microcode.c"
 164 #include "cpu/amd/model_10xxx/update_microcode.c"
 165
 166 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 167 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 168 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 169 void write_GPIO(void)
 170 {
 171         pnp_enter_ext_func_mode(GPIO1_DEV);
 172         pnp_set_logical_device(GPIO1_DEV);
 173         pnp_write_config(GPIO1_DEV, 0x30, 0x01);
 174         pnp_write_config(GPIO1_DEV, 0x60, 0x00);
 175         pnp_write_config(GPIO1_DEV, 0x61, 0x00);
 176         pnp_write_config(GPIO1_DEV, 0x62, 0x00);
 177         pnp_write_config(GPIO1_DEV, 0x63, 0x00);
 178         pnp_write_config(GPIO1_DEV, 0x70, 0x00);
 179         pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
 180         pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
 181         pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
 182         pnp_exit_ext_func_mode(GPIO1_DEV);
 183
 184         pnp_enter_ext_func_mode(GPIO2_DEV);
 185         pnp_set_logical_device(GPIO2_DEV);
 186         pnp_write_config(GPIO2_DEV, 0x30, 0x01);
 187         pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
 188         pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
 189         pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
 190         pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
 191         pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
 192         pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
 193         pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
 194         pnp_exit_ext_func_mode(GPIO2_DEV);
 195
 196         pnp_enter_ext_func_mode(GPIO3_DEV);
 197         pnp_set_logical_device(GPIO3_DEV);
 198         pnp_write_config(GPIO3_DEV, 0x30, 0x00);
 199         pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
 200         pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
 201         pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
 202         pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
 203         pnp_exit_ext_func_mode(GPIO3_DEV);
 204 }
 205
 206 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 207 {
 208   struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 209
 210         u32 bsp_apicid = 0;
 211         u32 val;
 212         u32 wants_reset;
 213         msr_t msr;
 214
 215         if (!cpu_init_detectedx && boot_cpu()) {
 216                 /* Nothing special needs to be done to find bus 0 */
 217                 /* Allow the HT devices to be found */
 218
 219                 set_bsp_node_CHtExtNodeCfgEn();
 220                 enumerate_ht_chain();
 221
 222                 sio_setup();
 223
 224                 /* Setup the mcp55 */
 225                 mcp55_enable_rom();
 226         }
 227
 228   post_code(0x30);
 229
 230         if (bist == 0) {
 231                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 232         }
 233
 234   post_code(0x32);
 235
 236         pnp_enter_ext_func_mode(SERIAL_DEV);
 237         pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
 238         w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 239         pnp_exit_ext_func_mode(SERIAL_DEV);
 240
 241         uart_init();
 242         console_init();
 243         write_GPIO();
 244         printk_debug("\n");
 245
 246         /* Halt if there was a built in self test failure */
 247         report_bist_failure(bist);
 248
 249  val = cpuid_eax(1);
 250  printk_debug("BSP Family_Model: %08x \n", val);
 251  printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
 252  printk_debug("bsp_apicid = %02x \n", bsp_apicid);
 253  printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
 254
 255  /* Setup sysinfo defaults */
 256  set_sysinfo_in_ram(0);
 257
 258  update_microcode(val);
 259  post_code(0x33);
 260
 261  cpuSetAMDMSR();
 262  post_code(0x34);
 263
 264  amd_ht_init(sysinfo);
 265  post_code(0x35);
 266
 267  /* Setup nodes PCI space and start core 0 AP init. */
 268  finalize_node_setup(sysinfo);
 269
 270  /* Setup any mainboard PCI settings etc. */
 271  setup_mb_resource_map();
 272  post_code(0x36);
 273
 274  /* wait for all the APs core0 started by finalize_node_setup. */
 275  /* FIXME: A bunch of cores are going to start output to serial at once.
 276   * It would be nice to fixup prink spinlocks for ROM XIP mode.
 277   * I think it could be done by putting the spinlock flag in the cache
 278   * of the BSP located right after sysinfo.
 279   */
 280
 281         wait_all_core0_started();
 282 #if CONFIG_LOGICAL_CPUS==1
 283  /* Core0 on each node is configured. Now setup any additional cores. */
 284  printk_debug("start_other_cores()\n");
 285         start_other_cores();
 286  post_code(0x37);
 287         wait_all_other_cores_started(bsp_apicid);
 288 #endif
 289
 290  post_code(0x38);
 291
 292 #if FAM10_SET_FIDVID == 1
 293  msr = rdmsr(0xc0010071);
 294  printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 295
 296  /* FIXME: The sb fid change may survive the warm reset and only
 297   * need to be done once.*/
 298
 299         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 300  post_code(0x39);
 301
 302  if (!warm_reset_detect(0)) {      // BSP is node 0
 303    init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 304  } else {
 305    init_fidvid_stage2(bsp_apicid, 0);  // BSP is node 0
 306         }
 307
 308  post_code(0x3A);
 309
 310  /* show final fid and vid */
 311  msr=rdmsr(0xc0010071);
 312  printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 313 #endif
 314
 315  wants_reset = mcp55_early_setup_x();
 316
 317  /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 318  if (!warm_reset_detect(0)) {
 319    print_info("...WARM RESET...\n\n\n");
 320                 soft_reset();
 321    die("After soft_reset_x - shouldn't see this message!!!\n");
 322         }
 323
 324  if (wants_reset)
 325    printk_debug("mcp55_early_setup_x wanted additional reset!\n");
 326
 327  post_code(0x3B);
 328
 329 /* It's the time to set ctrl in sysinfo now; */
 330 printk_debug("fill_mem_ctrl()\n");
 331 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 332
 333 post_code(0x3D);
 334
 335 //printk_debug("enable_smbus()\n");
 336 //        enable_smbus(); /* enable in sio_setup */
 337
 338 post_code(0x3E);
 339
 340         memreset_setup();
 341
 342 post_code(0x40);
 343
 344
 345  printk_debug("raminit_amdmct()\n");
 346  raminit_amdmct(sysinfo);
 347  post_code(0x41);
 348
 349 // printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 350  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
 351  post_code(0x42);  // Should never see this post code.
 352
 353 }
 354