We call this cache as ram everywhere, so let's call it the same in Kconfig
[coreboot.git] / src / mainboard / supermicro / h8dmr / Kconfig
1 if BOARD_SUPERMICRO_H8DMR
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_F
7         select NORTHBRIDGE_AMD_AMDK8
8         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
9         select SOUTHBRIDGE_NVIDIA_MCP55
10         select SUPERIO_WINBOND_W83627HF
11         select HAVE_OPTION_TABLE
12         select HAVE_BUS_CONFIG
13         select HAVE_PIRQ_TABLE
14         select HAVE_MP_TABLE
15         select CACHE_AS_RAM
16         select HAVE_HARD_RESET
17         select LIFT_BSP_APIC_ID
18         select BOARD_ROMSIZE_KB_1024
19
20 config MAINBOARD_DIR
21         string
22         default supermicro/h8dmr
23
24 config DCACHE_RAM_BASE
25         hex
26         default 0xc8000
27
28 config DCACHE_RAM_SIZE
29         hex
30         default 0x08000
31
32 config DCACHE_RAM_GLOBAL_VAR_SIZE
33         hex
34         default 0x01000
35
36 config APIC_ID_OFFSET
37         hex
38         default 0x10
39
40 config MEM_TRAIN_SEQ
41         int
42         default 1
43
44 config SB_HT_CHAIN_ON_BUS0
45         int
46         default 2
47
48 config MAINBOARD_PART_NUMBER
49         string
50         default "H8DMR-i2"
51
52 config HW_MEM_HOLE_SIZEK
53         hex
54         default 0x100000
55
56 config MAX_CPUS
57         int
58         default 4
59
60 config MAX_PHYSICAL_CPUS
61         int
62         default 2
63
64 config HT_CHAIN_END_UNITID_BASE
65         hex
66         default 0x20
67
68 config HT_CHAIN_UNITID_BASE
69         hex
70         default 0x0
71
72 config SB_HT_CHAIN_ON_BUS0
73         int
74         default 2
75
76 config IRQ_SLOT_COUNT
77         int
78         default 11
79
80 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
81         hex
82         default 0x15d9
83
84 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
85         hex
86         default 0x1511
87
88 endif # BOARD_SUPERMICRO_H8DMR