src/mainboard/supermicro/h8dme/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## This program is free software; you can redistribute it and/or modify
   5 ## it under the terms of the GNU General Public License as published by
   6 ## the Free Software Foundation; either version 2 of the License, or
   7 ## (at your option) any later version.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14 ## You should have received a copy of the GNU General Public License
  15 ## along with this program; if not, write to the Free Software
  16 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  17 ##
  18
  19 ##
  20 ## Compute the location and size of where this firmware image
  21 ## (coreboot plus bootloader) will live in the boot rom chip.
  22 ##
  23 if USE_FAILOVER_IMAGE
  24         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  25         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  26 else
  27     if USE_FALLBACK_IMAGE
  28         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  29         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  30     else
  31         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  32         default ROM_SECTION_OFFSET = 0
  33     end
  34 end
  35
  36 ##
  37 ## Compute the start location and size size of
  38 ## The coreboot bootloader.
  39 ##
  40 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  41 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  42
  43 ##
  44 ## Compute where this copy of coreboot will start in the boot rom
  45 ##
  46 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  47
  48 ##
  49 ## Compute a range of ROM that can cached to speed up coreboot,
  50 ## execution speed.
  51 ##
  52 ## XIP_ROM_SIZE must be a power of 2.
  53 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  54 ##
  55 default XIP_ROM_SIZE=65536
  56
  57 if USE_FAILOVER_IMAGE
  58         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  59 else
  60     if USE_FALLBACK_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  62     else
  63         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  64     end
  65 end
  66
  67 arch i386 end
  68
  69 ##
  70 ## Build the objects we have code for in this directory.
  71 ##
  72
  73 driver mainboard.o
  74 #needed by irq_tables and mptable and acpi_tables
  75 object get_bus_conf.o
  76
  77 if HAVE_MP_TABLE object mptable.o end
  78 if HAVE_PIRQ_TABLE object irq_tables.o end
  79 #object reset.o
  80 if USE_DCACHE_RAM
  81
  82         if CONFIG_USE_INIT
  83                 makerule ./auto.o
  84                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  85                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  86                 end
  87         else
  88                 makerule ./auto.inc
  89                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  90                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
  91                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  92                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  93                 end
  94         end
  95
  96 end
  97
  98 if USE_FAILOVER_IMAGE
  99 else
 100     if CONFIG_AP_CODE_IN_CAR
 101         makerule ./apc_auto.o
 102                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 103                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 104         end
 105         ldscript /arch/i386/init/ldscript_apc.lb
 106     end
 107 end
 108
 109
 110 ##
 111 ## Build our 16 bit and 32 bit coreboot entry code
 112 ##
 113 if HAVE_FAILOVER_BOOT
 114     if USE_FAILOVER_IMAGE
 115         mainboardinit cpu/x86/16bit/entry16.inc
 116         ldscript /cpu/x86/16bit/entry16.lds
 117     end
 118 else
 119     if USE_FALLBACK_IMAGE
 120         mainboardinit cpu/x86/16bit/entry16.inc
 121         ldscript /cpu/x86/16bit/entry16.lds
 122     end
 123 end
 124
 125 mainboardinit cpu/x86/32bit/entry32.inc
 126
 127 if USE_DCACHE_RAM
 128         if CONFIG_USE_INIT
 129                 ldscript /cpu/x86/32bit/entry32.lds
 130         end
 131
 132         if CONFIG_USE_INIT
 133                 ldscript /cpu/amd/car/cache_as_ram.lds
 134         end
 135 end
 136
 137
 138 ##
 139 ## Build our reset vector (This is where coreboot is entered)
 140 ##
 141 if HAVE_FAILOVER_BOOT
 142     if USE_FAILOVER_IMAGE
 143         mainboardinit cpu/x86/16bit/reset16.inc
 144         ldscript /cpu/x86/16bit/reset16.lds
 145     else
 146         mainboardinit cpu/x86/32bit/reset32.inc
 147         ldscript /cpu/x86/32bit/reset32.lds
 148     end
 149 else
 150     if USE_FALLBACK_IMAGE
 151         mainboardinit cpu/x86/16bit/reset16.inc
 152         ldscript /cpu/x86/16bit/reset16.lds
 153     else
 154         mainboardinit cpu/x86/32bit/reset32.inc
 155         ldscript /cpu/x86/32bit/reset32.lds
 156     end
 157 end
 158
 159 ##
 160 ## Include an id string (For safe flashing)
 161 ##
 162 mainboardinit southbridge/nvidia/mcp55/id.inc
 163 ldscript /southbridge/nvidia/mcp55/id.lds
 164
 165 ##
 166 ## ROMSTRAP table for MCP55
 167 ##
 168 if HAVE_FAILOVER_BOOT
 169     if USE_FAILOVER_IMAGE
 170         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 171         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 172     end
 173 else
 174     if USE_FALLBACK_IMAGE
 175         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 176         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 177     end
 178 end
 179
 180 if USE_DCACHE_RAM
 181         ##
 182         ## Setup Cache-As-Ram
 183         ##
 184         mainboardinit cpu/amd/car/cache_as_ram.inc
 185 end
 186
 187 ###
 188 ### This is the early phase of coreboot startup
 189 ### Things are delicate and we test to see if we should
 190 ### failover to another image.
 191 ###
 192 if HAVE_FAILOVER_BOOT
 193     if USE_FAILOVER_IMAGE
 194         if USE_DCACHE_RAM
 195                 ldscript /arch/i386/lib/failover_failover.lds
 196         end
 197     end
 198 else
 199     if USE_FALLBACK_IMAGE
 200         if USE_DCACHE_RAM
 201                 ldscript /arch/i386/lib/failover.lds
 202         end
 203     end
 204 end
 205
 206 ##
 207 ## Setup RAM
 208 ##
 209 if USE_DCACHE_RAM
 210
 211         if CONFIG_USE_INIT
 212                 initobject auto.o
 213         else
 214                 mainboardinit ./auto.inc
 215         end
 216 end
 217
 218 ##
 219 ## Include the secondary Configuration files
 220 ##
 221 config chip.h
 222
 223 chip northbridge/amd/amdk8/root_complex
 224         device apic_cluster 0 on
 225                 chip cpu/amd/socket_F
 226                         device apic 0 on end
 227                 end
 228         end
 229         device pci_domain 0 on
 230                 chip northbridge/amd/amdk8 #mc0
 231                         device pci 18.0 on end
 232                         device pci 18.0 on end
 233                         device pci 18.0 on
 234                                 #  devices on link 0, link 0 == LDT 0
 235                                 chip southbridge/nvidia/mcp55
 236                                         device pci 0.0 on end   # HT
 237                                         device pci 1.0 on # LPC
 238                                                 chip superio/winbond/w83627hf
 239                                                         device pnp 2e.0 off #  Floppy
 240                                                                 io 0x60 = 0x3f0
 241                                                                 irq 0x70 = 6
 242                                                                 drq 0x74 = 2
 243                                                         end
 244                                                         device pnp 2e.1 off #  Parallel Port
 245                                                                 io 0x60 = 0x378
 246                                                                 irq 0x70 = 7
 247                                                         end
 248                                                         device pnp 2e.2 on #  Com1
 249                                                                 io 0x60 = 0x3f8
 250                                                                 irq 0x70 = 4
 251                                                         end
 252                                                         device pnp 2e.3 off #  Com2
 253                                                                 io 0x60 = 0x2f8
 254                                                                 irq 0x70 = 3
 255                                                         end
 256                                                         device pnp 2e.5 on #  Keyboard
 257                                                                 io 0x60 = 0x60
 258                                                                 io 0x62 = 0x64
 259                                                                 irq 0x70 = 1
 260                                                                 irq 0x72 = 12
 261                                                         end
 262                                                         device pnp 2e.6 off  # SFI
 263                                                                 io 0x62 = 0x100
 264                                                         end
 265                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 266                                                                 io 0x60 = 0x220
 267                                                                 io 0x62 = 0x300
 268                                                                 irq 0x70 = 9
 269                                                         end
 270                                                         device pnp 2e.8 off end #  WDTO_PLED
 271                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 272                                                         device pnp 2e.a off end #  ACPI
 273                                                         device pnp 2e.b on #  HW Monitor
 274                                                                 io 0x60 = 0x290
 275                                                                 irq 0x70 = 5
 276                                                         end
 277                                                 end
 278                                         end
 279                                         device pci 1.1 on # SM 0
 280                                                 chip drivers/i2c/i2cmux2
 281                                                         device i2c 48 off end
 282                                                         device i2c 49 off end
 283                                                 end
 284                                         end # SM
 285                                         device pci 1.1 on # SM 1
 286 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 287 #                                                chip drivers/generic/generic #PCIXA Slot1
 288 #                                                        device i2c 50 on end
 289 #                                                end
 290 #                                                chip drivers/generic/generic #PCIXB Slot1
 291 #                                                        device i2c 51 on end
 292 #                                                end
 293 #                                                chip drivers/generic/generic #PCIXB Slot2
 294 #                                                        device i2c 52 on end
 295 #                                                end
 296 #                                                chip drivers/generic/generic #PCI Slot1
 297 #                                                        device i2c 53 on end
 298 #                                                end
 299 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 300 #                                                        device i2c 54 on end
 301 #                                                end
 302 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 303 #                                                        device i2c 55 on end
 304 #                                                end
 305                                                 chip drivers/generic/generic #MAC EEPROM
 306                                                         device i2c 51 on end
 307                                                 end
 308
 309                                         end # SM
 310                                         device pci 2.0 on end # USB 1.1
 311                                         device pci 2.1 on end # USB 2
 312                                         device pci 4.0 on end # IDE
 313                                         device pci 5.0 on end # SATA 0
 314                                         device pci 5.1 on end # SATA 1
 315                                         device pci 5.2 on end # SATA 2
 316                                         device pci 6.0 on  # PCI
 317                                                 chip drivers/pci/onboard
 318                                                         device pci 6.0 on end
 319                                                         register "rom_address" = "0xfff00000" #for 1M
 320 #                                                        register "rom_address" = "0xfff80000" #for 512K
 321                                                 end
 322                                         end
 323                                         device pci 6.1 on end # AZA
 324                                         device pci 8.0 on end # NIC
 325                                         device pci 9.0 on end # NIC
 326                                         device pci a.0 on  # PCI E 5
 327                                                 device pci 0.0 on #nec pci-x
 328                                                 end
 329                                                 device pci 0.1 on #nec pci-x
 330                                                         device pci 4.0 on end #scsi
 331                                                         device pci 4.1 on end #scsi
 332                                                 end
 333                                         end
 334                                         device pci b.0 on end # PCI E 4
 335                                         device pci c.0 on end # PCI E 3
 336                                         device pci d.0 on end # PCI E 2
 337                                         device pci e.0 on end # PCI E 1
 338                                         device pci f.0 on end # PCI E 0
 339                                         register "ide0_enable" = "1"
 340                                         register "sata0_enable" = "1"
 341                                         register "sata1_enable" = "1"
 342                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 343                                         register "mac_eeprom_addr" = "0x51"
 344                                 end
 345                         end #  device pci 18.0
 346                         device pci 18.1 on end
 347                         device pci 18.2 on end
 348                         device pci 18.3 on end
 349                 end # mc0
 350
 351         end # PCI domain
 352
 353 #       chip drivers/generic/debug
 354 #               device pnp 0.0 off end # chip name
 355 #                device pnp 0.1 on end # pci_regs_all
 356 #                device pnp 0.2 off end # mem
 357 #                device pnp 0.3 off end # cpuid
 358 #                device pnp 0.4 on end # smbus_regs_all
 359 #                device pnp 0.5 off end # dual core msr
 360 #                device pnp 0.6 off end # cache size
 361 #                device pnp 0.7 off end # tsc
 362 #                device pnp 0.8 off  end # io
 363 #                device pnp 0.9 on end # io
 364 #       end
 365 end #root_complex