1 #define K8_ALLOCATE_IO_RANGE 1
3 #define QRANK_DIMM_SUPPORT 1
5 #if CONFIG_LOGICAL_CPUS==1
6 #define SET_NB_CFG_54 1
12 #include <device/pci_def.h>
14 #include <device/pnp_def.h>
15 #include <arch/romcc_io.h>
16 #include <cpu/x86/lapic.h>
17 #include "option_table.h"
18 #include "pc80/mc146818rtc_early.c"
19 #include "pc80/serial.c"
20 #include "console/console.c"
21 #include "lib/ramtest.c"
23 #include <cpu/amd/model_fxx_rev.h>
24 #include "northbridge/amd/amdk8/incoherent_ht.c"
25 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
26 #include "northbridge/amd/amdk8/raminit.h"
27 #include "cpu/amd/model_fxx/apic_timer.c"
28 #include "lib/delay.c"
30 #include "cpu/x86/lapic/boot_cpu.c"
31 #include "northbridge/amd/amdk8/reset_test.c"
32 #include "northbridge/amd/amdk8/debug.c"
33 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
35 #include "cpu/amd/mtrr/amd_earlymtrr.c"
36 #include "cpu/x86/bist.h"
38 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
40 #include "northbridge/amd/amdk8/setup_resource_map.c"
42 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
44 static void memreset_setup(void)
48 static void memreset(int controllers, const struct mem_controller *ctrl)
52 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
54 #define SUPERIO_GPIO_IO_BASE 0x400
56 static void sio_gpio_setup(void){
60 /*Enable onboard scsi*/
61 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
62 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
63 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
67 static inline void activate_spd_rom(const struct mem_controller *ctrl)
72 static inline int spd_read_byte(unsigned device, unsigned address)
74 return smbus_read_byte(device, address);
77 #include "northbridge/amd/amdk8/raminit.c"
78 #include "northbridge/amd/amdk8/coherent_ht.c"
79 #include "lib/generic_sdram.c"
81 /* tyan does not want the default */
82 #include "resourcemap.c"
84 #include "cpu/amd/dualcore/dualcore.c"
87 #define CK804_USE_NIC 1
88 #define CK804_USE_ACI 1
90 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
92 //set GPIO to input mode
93 #define CK804_MB_SETUP \
94 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
95 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
96 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
97 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
98 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
99 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
101 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
103 #include "cpu/amd/car/copy_and_run.c"
105 #include "cpu/amd/car/post_cache_as_ram.c"
107 #include "cpu/amd/model_fxx/init_cpus.c"
109 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
110 #include "northbridge/amd/amdk8/early_ht.c"
112 static void sio_setup(void)
120 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
122 byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
124 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
126 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
127 dword |= (1<<29)|(1<<0);
128 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
131 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
133 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
135 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
140 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
142 static const uint16_t spd_addr [] = {
143 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
144 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
145 #if CONFIG_MAX_PHYSICAL_CPUS > 1
146 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
147 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
152 unsigned bsp_apicid = 0;
154 struct mem_controller ctrl[8];
157 if (!cpu_init_detectedx && boot_cpu()) {
158 /* Nothing special needs to be done to find bus 0 */
159 /* Allow the HT devices to be found */
161 enumerate_ht_chain();
165 /* Setup the ck804 */
170 bsp_apicid = init_cpus(cpu_init_detectedx);
173 lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
177 /* Halt if there was a built in self test failure */
178 report_bist_failure(bist);
180 setup_ultra40_resource_map();
182 needs_reset = setup_coherent_ht_domain();
184 wait_all_core0_started();
185 #if CONFIG_LOGICAL_CPUS==1
186 // It is said that we should start core1 after all core0 launched
188 wait_all_other_cores_started(bsp_apicid);
191 needs_reset |= ht_setup_chains_x();
193 needs_reset |= ck804_early_setup_x();
196 print_info("ht reset -\r\n");
200 allow_all_aps_stop(bsp_apicid);
203 //It's the time to set ctrl now;
204 fill_mem_ctrl(nodes, ctrl, spd_addr);
209 sdram_initialize(nodes, ctrl);