src/mainboard/sunw/ultra40/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4
   5 #define K8_ALLOCATE_IO_RANGE 1
   6 //#define K8_SCAN_PCI_BUS 1
   7
   8
   9 #define QRANK_DIMM_SUPPORT 1
  10
  11 #if CONFIG_LOGICAL_CPUS==1
  12 #define SET_NB_CFG_54 1
  13 #endif
  14
  15
  16 #include <stdint.h>
  17 #include <device/pci_def.h>
  18 #include <arch/io.h>
  19 #include <device/pnp_def.h>
  20 #include <arch/romcc_io.h>
  21 #include <cpu/x86/lapic.h>
  22 #include "option_table.h"
  23 #include "pc80/mc146818rtc_early.c"
  24 #include "pc80/serial.c"
  25 #include "arch/i386/lib/console.c"
  26 #include "ram/ramtest.c"
  27
  28 #include <cpu/amd/model_fxx_rev.h>
  29 #include "northbridge/amd/amdk8/incoherent_ht.c"
  30 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33 #include "lib/delay.c"
  34
  35 #if CONFIG_USE_INIT == 0
  36 #include "lib/memcpy.c"
  37 #endif
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  43
  44 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46
  47 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  52
  53 static void memreset_setup(void)
  54 {
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  62
  63 #define SUPERIO_GPIO_IO_BASE 0x400
  64
  65 static void sio_gpio_setup(void){
  66
  67         unsigned value;
  68
  69         /*Enable onboard scsi*/
  70         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  71         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  72         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  73
  74 }
  75
  76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  77 {
  78         /* nothing to do */
  79 }
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86
  87 #include "northbridge/amd/amdk8/raminit.c"
  88 #include "northbridge/amd/amdk8/coherent_ht.c"
  89 #include "sdram/generic_sdram.c"
  90
  91  /* tyan does not want the default */
  92 #include "resourcemap.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95
  96 #define CK804_NUM 2
  97 #define CK804_USE_NIC 1
  98 #define CK804_USE_ACI 1
  99
 100 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 101
 102 //set GPIO to input mode
 103 #define CK804_MB_SETUP \
 104                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 105                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 106                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 107                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 108                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 109                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 110
 111 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 112
 113 #include "cpu/amd/car/copy_and_run.c"
 114
 115 #include "cpu/amd/car/post_cache_as_ram.c"
 116
 117 #include "cpu/amd/model_fxx/init_cpus.c"
 118
 119
 120 #if USE_FALLBACK_IMAGE == 1
 121
 122 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 123 #include "northbridge/amd/amdk8/early_ht.c"
 124
 125
 126 static void sio_setup(void)
 127 {
 128
 129         unsigned value;
 130         uint32_t dword;
 131         uint8_t byte;
 132
 133
 134         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 135
 136         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 137         byte |= 0x20;
 138         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 139
 140         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 141         dword |= (1<<29)|(1<<0);
 142         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 143
 144 #if  1
 145         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 146
 147         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 148         value &= 0xbf;
 149         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 150 #endif
 151
 152 }
 153
 154 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 155 {
 156         unsigned last_boot_normal_x = last_boot_normal();
 157
 158         /* Is this a cpu only reset? or Is this a secondary cpu? */
 159         if ((cpu_init_detectedx) || (!boot_cpu())) {
 160                 if (last_boot_normal_x) {
 161                         goto normal_image;
 162                 } else {
 163                         goto fallback_image;
 164                 }
 165         }
 166
 167         /* Nothing special needs to be done to find bus 0 */
 168         /* Allow the HT devices to be found */
 169
 170         enumerate_ht_chain();
 171
 172         sio_setup();
 173
 174         /* Setup the ck804 */
 175         ck804_enable_rom();
 176
 177         /* Is this a deliberate reset by the bios */
 178         if (bios_reset_detected() && last_boot_normal_x) {
 179                 goto normal_image;
 180         }
 181         /* This is the primary cpu how should I boot? */
 182         else if (do_normal_boot()) {
 183                 goto normal_image;
 184         }
 185         else {
 186                 goto fallback_image;
 187         }
 188  normal_image:
 189         __asm__ volatile ("jmp __normal_image"
 190                 : /* outputs */
 191                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 192                 );
 193
 194  fallback_image:
 195         ;
 196 }
 197 #endif
 198
 199 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 200
 201 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 202 {
 203
 204 #if USE_FALLBACK_IMAGE == 1
 205         failover_process(bist, cpu_init_detectedx);
 206 #endif
 207         real_main(bist, cpu_init_detectedx);
 208
 209 }
 210
 211 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 212 {
 213         static const uint16_t spd_addr [] = {
 214                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 215                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 216 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 217                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 218                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 219 #endif
 220         };
 221
 222         int needs_reset;
 223         unsigned bsp_apicid = 0;
 224
 225         struct mem_controller ctrl[8];
 226         unsigned nodes;
 227
 228         if (bist == 0) {
 229                 bsp_apicid = init_cpus(cpu_init_detectedx);
 230         }
 231
 232         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 233         uart_init();
 234         console_init();
 235
 236         /* Halt if there was a built in self test failure */
 237         report_bist_failure(bist);
 238
 239         setup_ultra40_resource_map();
 240
 241         needs_reset = setup_coherent_ht_domain();
 242
 243         wait_all_core0_started();
 244 #if CONFIG_LOGICAL_CPUS==1
 245         // It is said that we should start core1 after all core0 launched
 246         start_other_cores();
 247         wait_all_other_cores_started(bsp_apicid);
 248 #endif
 249
 250         needs_reset |= ht_setup_chains_x();
 251
 252         needs_reset |= ck804_early_setup_x();
 253
 254         if (needs_reset) {
 255                 print_info("ht reset -\r\n");
 256                 soft_reset();
 257         }
 258
 259         allow_all_aps_stop(bsp_apicid);
 260
 261         nodes = get_nodes();
 262         //It's the time to set ctrl now;
 263         fill_mem_ctrl(nodes, ctrl, spd_addr);
 264
 265         enable_smbus();
 266
 267         memreset_setup();
 268         sdram_initialize(nodes, ctrl);
 269
 270         post_cache_as_ram();
 271 }