src/mainboard/sunw/ultra40/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include <stdlib.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 //#define K8_HT_FREQ_1G_SUPPORT 1
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include <cpu/amd/model_fxx_msr.h>
  28 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  29
  30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32 #include "cpu/amd/dualcore/dualcore.c"
  33
  34 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  39
  40 static void hard_reset(void)
  41 {
  42         set_bios_reset();
  43
  44         /* full reset */
  45         outb(0x0a, 0x0cf9);
  46         outb(0x0e, 0x0cf9);
  47 }
  48
  49 static void soft_reset(void)
  50 {
  51         set_bios_reset();
  52 #if 1
  53         /* link reset */
  54         outb(0x02, 0x0cf9);
  55         outb(0x06, 0x0cf9);
  56 #endif
  57 }
  58
  59 static void memreset_setup(void)
  60 {
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  68
  69 #define SUPERIO_GPIO_IO_BASE 0x400
  70
  71 static void sio_gpio_setup(void){
  72
  73         unsigned value;
  74
  75 //      lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
  76
  77 #if 1
  78         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  79         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  80         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  81 #endif
  82
  83 }
  84
  85 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  86 {
  87         /* nothing to do */
  88 }
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 #define QRANK_DIMM_SUPPORT 1
  96
  97 #include "northbridge/amd/amdk8/raminit.c"
  98 #if 0
  99         #define ENABLE_APIC_EXT_ID 1
 100         #define APIC_ID_OFFSET 0x10
 101         #define LIFT_BSP_APIC_ID 0
 102 #else
 103         #define ENABLE_APIC_EXT_ID 0
 104 #endif
 105 #include "northbridge/amd/amdk8/coherent_ht.c"
 106 #include "sdram/generic_sdram.c"
 107
 108 /* maybe does not want the default */
 109 #include "resourcemap.c"
 110
 111
 112 #define FIRST_CPU  1
 113 #define SECOND_CPU 1
 114 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 115
 116 #define CK804_NUM 2
 117 #define CK804B_BUSN 0x80
 118 #define CK804_USE_NIC 1
 119 #define CK804_USE_ACI 1
 120 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 121
 122 //set GPIO to input mode
 123 #define CK804_MB_SETUP \
 124                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 125                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 126                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 127                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 128                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 129                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 130
 131 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 132
 133
 134 static void main(unsigned long bist)
 135 {
 136         static const struct mem_controller cpu[] = {
 137 #if FIRST_CPU
 138                 {
 139                         .node_id = 0,
 140                         .f0 = PCI_DEV(0, 0x18, 0),
 141                         .f1 = PCI_DEV(0, 0x18, 1),
 142                         .f2 = PCI_DEV(0, 0x18, 2),
 143                         .f3 = PCI_DEV(0, 0x18, 3),
 144                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 145                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 146                 },
 147 #endif
 148 #if SECOND_CPU
 149                 {
 150                         .node_id = 1,
 151                         .f0 = PCI_DEV(0, 0x19, 0),
 152                         .f1 = PCI_DEV(0, 0x19, 1),
 153                         .f2 = PCI_DEV(0, 0x19, 2),
 154                         .f3 = PCI_DEV(0, 0x19, 3),
 155                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 156                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 157                 },
 158 #endif
 159         };
 160
 161         int needs_reset;
 162
 163         if (bist == 0) {
 164                 k8_init_and_stop_secondaries();
 165         }
 166
 167         // post_code(0x32);
 168
 169         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 170         uart_init();
 171         console_init();
 172
 173         /* Halt if there was a built in self test failure */
 174         report_bist_failure(bist);
 175
 176         sio_gpio_setup();
 177
 178         setup_ultra40_resource_map();
 179
 180         needs_reset = setup_coherent_ht_domain();
 181
 182         needs_reset |= ht_setup_chains_x();
 183
 184         needs_reset |= ck804_early_setup_x();
 185
 186         if (needs_reset) {
 187                 print_info("ht reset -\r\n");
 188                 soft_reset();
 189         }
 190
 191
 192         enable_smbus();
 193
 194         memreset_setup();
 195         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 196
 197
 198 }