2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
26 #include <arch/romcc_io.h>
28 #include <console/console.h>
30 #include "cpu/x86/bist.h"
31 #include "cpu/x86/msr.h"
32 #include <cpu/amd/lxdef.h>
33 #include "southbridge/amd/cs5536/cs5536.h"
35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
37 /* The ALIX.2D has no SMBus; the setup is hard-wired. */
38 static void cs5536_enable_smbus(void) { }
40 #include "southbridge/amd/cs5536/early_setup.c"
42 /* The part is a Hynix hy5du121622ctp-d43.
44 * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
47 * VDD 2.5 VDDQ 2.5 (U)
48 * 512M 8K REFRESH (12)
53 * Normal Power Consumption (<blank> )
55 * Single Die (<blank>)
60 static const u8 spdbytes[] = {
61 [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
62 [SPD_BANK_DENSITY] = 0x40,
63 [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
64 [SPD_MEMORY_TYPE] = 7,
65 [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
66 [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
67 [SPD_NUM_BANKS_PER_SDRAM] = 4,
68 [SPD_PRIMARY_SDRAM_WIDTH] = 8,
69 [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
70 [SPD_NUM_COLUMNS] = 0xa,
73 [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
74 [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
82 static u8 spd_read_byte(u8 device, u8 address)
84 print_debug("spd_read_byte dev ");
85 print_debug_hex8(device);
87 if (device != DIMM0) {
88 print_debug(" returns 0xff\n");
92 print_debug(" addr ");
93 print_debug_hex8(address);
94 print_debug(" returns ");
95 print_debug_hex8(spdbytes[address]);
98 return spdbytes[address];
101 #define ManualConf 0 /* Do automatic strapped PLL config */
102 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
103 #define PLLMSRlo 0x02000030
105 #include "northbridge/amd/lx/raminit.h"
106 #include "northbridge/amd/lx/pll_reset.c"
107 #include "northbridge/amd/lx/raminit.c"
108 #include "lib/generic_sdram.c"
109 #include "cpu/amd/model_lx/cpureginit.c"
110 #include "cpu/amd/model_lx/syspreinit.c"
111 #include "cpu/amd/model_lx/msrinit.c"
113 /** Early mainboard specific GPIO setup. */
114 static void mb_gpio_init(void)
117 * Enable LEDs GPIO outputs to light up the leds
118 * This is how the original tinyBIOS sets them after boot.
119 * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it
120 * may be used here, but not after PCI Init.
121 * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the
122 * leds-alix2.c driver. Coreboot dynamically assigns this space,
123 * so the driver does not work anymore.
124 * Good workaround: use the newer driver
125 * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
126 * This resets the GPIO I/O space to 0x6100.
127 * This may break other things, though.
129 outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
130 outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
131 outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
133 /* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
134 outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
135 outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
138 void main(unsigned long bist)
140 static const struct mem_controller memctrl[] = {
141 {.channel0 = {DIMM0}},
147 cs5536_early_setup();
149 /* NOTE: Must do this AFTER cs5536_early_setup()!
150 * It is counting on some early MSR setup for the CS5536.
152 cs5536_setup_onchipuart(1);
156 /* Halt if there was a built in self test failure */
157 report_bist_failure(bist);
159 pll_reset(ManualConf);
161 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
163 sdram_initialize(1, memctrl);
165 /* Switch from Cache as RAM to real RAM.
167 * There are two ways we could think about this.
169 * 1. If we are using the romstage.inc ROMCC way, the stack is
170 * going to be re-setup in the code following this code. Just
171 * wbinvd the stack to clear the cache tags. We don't care
172 * where the stack used to be.
174 * 2. This file is built as a normal .c -> .o and linked in
175 * etc. The stack might be used to return etc. That means we
176 * care about what is in the stack. If we are smart we set
177 * the CAR stack to the same location as the rest of
178 * coreboot. If that is the case we can just do a wbinvd.
179 * The stack will be written into real RAM that is now setup
180 * and we continue like nothing happened. If the stack is
181 * located somewhere other than where LB would like it, you
182 * need to write some code to do a copy from cache to RAM
184 * We use method 1 on Norwich and on this board too.
187 print_err("POST 02\n");
189 print_err("Past wbinvd\n");
191 /* We are finding the return does not work on this board. Explicitly
192 * call the label that is after the call to us. This is gross, but
193 * sometimes at this level it is the only way out.
195 void done_cache_as_ram_main(void);
196 done_cache_as_ram_main();