2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <device/pci_def.h>
24 #include <device/pnp_def.h>
25 #include <arch/romcc_io.h>
27 #include "pc80/serial.c"
28 #include "console/console.c"
29 #include "lib/ramtest.c"
30 #include "cpu/x86/bist.h"
31 #include "cpu/x86/msr.h"
32 #include <cpu/amd/lxdef.h>
33 #include <cpu/amd/geode_post_code.h>
34 #include "southbridge/amd/cs5536/cs5536.h"
36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
38 /* The ALIX1.C has no SMBus; the setup is hard-wired. */
39 void cs5536_enable_smbus(void)
43 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
46 /* The part is a Hynix hy5du121622ctp-d43.
48 * HY 5D U 12 16 2 2 C <blank> T <blank> P D43
51 * VDD 2.5 VDDQ 2.5 (U)
52 * 512M 8K REFRESH (12)
57 * Normal Power Consumption (<blank> )
59 * Single Die (<blank>)
64 static const u8 spdbytes[] = {
65 [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10,
66 [SPD_BANK_DENSITY] = 0x40,
67 [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff,
68 [SPD_MEMORY_TYPE] = 7,
69 [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */
70 [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */
71 [SPD_NUM_BANKS_PER_SDRAM] = 4,
72 [SPD_PRIMARY_SDRAM_WIDTH] = 8,
73 [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */
74 [SPD_NUM_COLUMNS] = 0xa,
77 [SPD_SDRAM_CYCLE_TIME_2ND] = 60,
78 [SPD_SDRAM_CYCLE_TIME_3RD] = 75,
86 static u8 spd_read_byte(u8 device, u8 address)
88 print_debug("spd_read_byte dev ");
89 print_debug_hex8(device);
91 if (device != (0x50 << 1)) {
92 print_debug(" returns 0xff\n");
96 print_debug(" addr ");
97 print_debug_hex8(address);
98 print_debug(" returns ");
99 print_debug_hex8(spdbytes[address]);
102 return spdbytes[address];
105 #define ManualConf 0 /* Do automatic strapped PLL config */
106 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
107 #define PLLMSRlo 0x02000030
112 #include "northbridge/amd/lx/raminit.h"
113 #include "northbridge/amd/lx/pll_reset.c"
114 #include "northbridge/amd/lx/raminit.c"
115 #include "lib/generic_sdram.c"
116 #include "cpu/amd/model_lx/cpureginit.c"
117 #include "cpu/amd/model_lx/syspreinit.c"
119 static void msr_init(void)
123 /* Setup access to the MC for under 1MB. Note MC not setup yet. */
126 wrmsr(CPU_RCONF_DEFAULT, msr);
130 wrmsr(MSR_GLIU0 + 0x20, msr);
134 wrmsr(MSR_GLIU1 + 0x20, msr);
137 /** Early mainboard specific GPIO setup. */
138 static void mb_gpio_init(void)
142 void cache_as_ram_main(void)
144 static const struct mem_controller memctrl[] = {
145 {.channel0 = {0x50}},
153 cs5536_early_setup();
155 /* NOTE: Must do this AFTER cs5536_early_setup()!
156 * It is counting on some early MSR setup for the CS5536.
158 cs5536_disable_internal_uart();
159 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
164 pll_reset(ManualConf);
168 sdram_initialize(1, memctrl);
171 /* Enable this only if you are having questions. */
172 /* ram_check(0, 640 * 1024); */
174 /* Switch from Cache as RAM to real RAM.
176 * There are two ways we could think about this.
178 * 1. If we are using the romstage.inc ROMCC way, the stack is
179 * going to be re-setup in the code following this code. Just
180 * wbinvd the stack to clear the cache tags. We don't care
181 * where the stack used to be.
183 * 2. This file is built as a normal .c -> .o and linked in
184 * etc. The stack might be used to return etc. That means we
185 * care about what is in the stack. If we are smart we set
186 * the CAR stack to the same location as the rest of
187 * coreboot. If that is the case we can just do a wbinvd.
188 * The stack will be written into real RAM that is now setup
189 * and we continue like nothing happened. If the stack is
190 * located somewhere other than where LB would like it, you
191 * need to write some code to do a copy from cache to RAM
193 * We use method 1 on Norwich and on this board too.
196 print_err("POST 02\n");
198 print_err("Past wbinvd\n");
200 /* We are finding the return does not work on this board. Explicitly
201 * call the label that is after the call to us. This is gross, but
202 * sometimes at this level it is the only way out.
204 void done_cache_as_ram_main(void);
205 done_cache_as_ram_main();