2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006-2007 Ronald G. Minnich <rminnich@gmail.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 uses CONFIG_HAVE_MP_TABLE
23 uses CONFIG_HAVE_PIRQ_TABLE
24 uses CONFIG_USE_FALLBACK_IMAGE
25 uses CONFIG_HAVE_FALLBACK_BOOT
26 uses CONFIG_HAVE_HARD_RESET
27 uses CONFIG_HAVE_OPTION_TABLE
28 uses CONFIG_USE_OPTION_TABLE
29 uses CONFIG_ROM_PAYLOAD
30 uses CONFIG_IRQ_SLOT_COUNT
32 uses CONFIG_MAINBOARD_VENDOR
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses COREBOOT_EXTRA_VERSION
36 uses CONFIG_FALLBACK_SIZE
37 uses CONFIG_STACK_SIZE
40 uses CONFIG_ROM_SECTION_SIZE
41 uses CONFIG_ROM_IMAGE_SIZE
42 uses CONFIG_ROM_SECTION_SIZE
43 uses CONFIG_ROM_SECTION_OFFSET
44 uses CONFIG_ROM_PAYLOAD_START
45 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
46 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
47 uses CONFIG_PRECOMPRESSED_PAYLOAD
48 uses CONFIG_PAYLOAD_SIZE
51 uses CONFIG_XIP_ROM_SIZE
52 uses CONFIG_XIP_ROM_BASE
53 uses CONFIG_HAVE_MP_TABLE
54 uses CONFIG_CROSS_COMPILE
58 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
59 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
60 uses CONFIG_CONSOLE_SERIAL8250
61 uses CONFIG_TTYS0_BAUD
62 uses CONFIG_TTYS0_BASE
64 uses CONFIG_UDELAY_TSC
65 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
66 uses CONFIG_CONSOLE_VGA
67 uses CONFIG_PCI_ROM_RUN
69 uses CONFIG_USE_DCACHE_RAM
70 uses CONFIG_DCACHE_RAM_BASE
71 uses CONFIG_DCACHE_RAM_SIZE
72 uses CONFIG_USE_PRINTK_IN_CAR
73 uses CONFIG_PIRQ_ROUTE
75 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
76 default CONFIG_ROM_SIZE = 512*1024
81 default CONFIG_CONSOLE_VGA=0
82 default CONFIG_VIDEO_MB=8
83 default CONFIG_PCI_ROM_RUN=0
86 ## Build code for the fallback boot
88 default CONFIG_HAVE_FALLBACK_BOOT=1
93 default CONFIG_HAVE_MP_TABLE=0
96 ## Build code to reset the motherboard from coreboot
98 default CONFIG_HAVE_HARD_RESET=0
100 ## Delay timer options
102 default CONFIG_UDELAY_TSC=1
103 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
106 ## Build code to export a programmable irq routing table
108 default CONFIG_HAVE_PIRQ_TABLE=1
109 default CONFIG_IRQ_SLOT_COUNT=5
110 default CONFIG_PIRQ_ROUTE=1
112 ## Build code to export a CMOS option table
114 default CONFIG_HAVE_OPTION_TABLE=0
117 ### coreboot layout values
120 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
121 default CONFIG_ROM_IMAGE_SIZE = 65536
122 default CONFIG_FALLBACK_SIZE = 131072
125 ## enable CACHE_AS_RAM specifics
127 default CONFIG_USE_DCACHE_RAM=1
128 default CONFIG_DCACHE_RAM_BASE=0xc8000
129 default CONFIG_DCACHE_RAM_SIZE=0x08000
130 default CONFIG_USE_PRINTK_IN_CAR=1
133 ## Use a small 8K stack
135 default CONFIG_STACK_SIZE=0x2000
138 ## Use a small 16K heap
140 default CONFIG_HEAP_SIZE=0x4000
143 ## Only use the option table in a normal image
145 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
146 default CONFIG_USE_OPTION_TABLE = 0
148 default CONFIG_RAMBASE = 0x00004000
150 default CONFIG_ROM_PAYLOAD = 1
153 ## The default compiler
155 default CONFIG_CROSS_COMPILE=""
156 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
157 default CONFIG_HOSTCC="gcc"
160 ## The Serial Console
163 # To Enable the Serial Console
164 default CONFIG_CONSOLE_SERIAL8250=1
166 ## Select the serial console baud rate
167 default CONFIG_TTYS0_BAUD=115200
168 #default CONFIG_TTYS0_BAUD=57600
169 #default CONFIG_TTYS0_BAUD=38400
170 #default CONFIG_TTYS0_BAUD=19200
171 #default CONFIG_TTYS0_BAUD=9600
172 #default CONFIG_TTYS0_BAUD=4800
173 #default CONFIG_TTYS0_BAUD=2400
174 #default CONFIG_TTYS0_BAUD=1200
176 # Select the serial console base port
177 default CONFIG_TTYS0_BASE=0x3f8
179 # Select the serial protocol
180 # This defaults to 8 data bits, 1 stop bit, and no parity
181 default CONFIG_TTYS0_LCS=0x3
184 ### Select the coreboot loglevel
186 ## EMERG 1 system is unusable
187 ## ALERT 2 action must be taken immediately
188 ## CRIT 3 critical conditions
189 ## ERR 4 error conditions
190 ## WARNING 5 warning conditions
191 ## NOTICE 6 normal but significant condition
192 ## INFO 7 informational
193 ## CONFIG_DEBUG 8 debug-level messages
194 ## SPEW 9 Way too many details
196 ## Request this level of debugging output
197 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
198 ## At a maximum only compile in this level of debugging
199 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
206 default CONFIG_CBFS=0