src/mainboard/newisys/khepri/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 if USE_DCACHE_RAM
  51
  52 if CONFIG_USE_INIT
  53
  54 makerule ./auto.o
  55         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  56         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  57 end
  58
  59 else
  60
  61 makerule ./auto.inc
  62         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  63         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  64         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  65         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  66 end
  67
  68 end
  69 else
  70
  71 ##
  72 ## Romcc output
  73 ##
  74 makerule ./failover.E
  75         depends "$(MAINBOARD)/failover.c ./romcc"
  76         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  77 end
  78
  79 makerule ./failover.inc
  80         depends "$(MAINBOARD)/failover.c ./romcc"
  81         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  82 end
  83
  84 makerule ./auto.E
  85         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  86         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  87 end
  88 makerule ./auto.inc
  89         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  90         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  91 end
  92
  93 end
  94
  95 ##
  96 ## Build our 16 bit and 32 bit coreboot entry code
  97 ##
  98 if USE_FALLBACK_IMAGE
  99         mainboardinit cpu/x86/16bit/entry16.inc
 100         ldscript /cpu/x86/16bit/entry16.lds
 101 end
 102
 103 mainboardinit cpu/x86/32bit/entry32.inc
 104
 105 if USE_DCACHE_RAM
 106         if CONFIG_USE_INIT
 107                 ldscript /cpu/x86/32bit/entry32.lds
 108         end
 109
 110         if CONFIG_USE_INIT
 111                 ldscript      /cpu/amd/car/cache_as_ram.lds
 112         end
 113 end
 114
 115 ##
 116 ## Build our reset vector (This is where coreboot is entered)
 117 ##
 118 if USE_FALLBACK_IMAGE
 119         mainboardinit cpu/x86/16bit/reset16.inc
 120         ldscript /cpu/x86/16bit/reset16.lds
 121 else
 122         mainboardinit cpu/x86/32bit/reset32.inc
 123         ldscript /cpu/x86/32bit/reset32.lds
 124 end
 125
 126 ### Should this be in the northbridge code?
 127 if USE_DCACHE_RAM
 128 else
 129 mainboardinit arch/i386/lib/cpu_reset.inc
 130 end
 131 ##
 132 ## Include an id string (For safe flashing)
 133 ##
 134 mainboardinit arch/i386/lib/id.inc
 135 ldscript /arch/i386/lib/id.lds
 136
 137 if USE_DCACHE_RAM
 138 ##
 139 ## Setup Cache-As-Ram
 140 ##
 141 mainboardinit cpu/amd/car/cache_as_ram.inc
 142 end
 143
 144 ###
 145 ### This is the early phase of coreboot startup
 146 ### Things are delicate and we test to see if we should
 147 ### failover to another image.
 148 ###
 149 if USE_FALLBACK_IMAGE
 150 if USE_DCACHE_RAM
 151         ldscript /arch/i386/lib/failover.lds
 152 else
 153         ldscript /arch/i386/lib/failover.lds
 154         mainboardinit ./failover.inc
 155 end
 156 end
 157
 158 ###
 159 ### O.k. We aren't just an intermediary anymore!
 160 ###
 161
 162 ##
 163 ## Setup RAM
 164 ##
 165 if USE_DCACHE_RAM
 166
 167 if CONFIG_USE_INIT
 168 initobject auto.o
 169 else
 170 mainboardinit ./auto.inc
 171 end
 172
 173 else
 174
 175 ##
 176 ## Setup RAM
 177 ##
 178
 179 mainboardinit cpu/x86/fpu/enable_fpu.inc
 180 mainboardinit cpu/x86/mmx/enable_mmx.inc
 181 mainboardinit cpu/x86/sse/enable_sse.inc
 182 mainboardinit ./auto.inc
 183 mainboardinit cpu/x86/sse/disable_sse.inc
 184 mainboardinit cpu/x86/mmx/disable_mmx.inc
 185
 186 end
 187
 188 config chip.h
 189
 190 # FIXME: ROM for onboard VGA
 191
 192 chip northbridge/amd/amdk8/root_complex
 193         device apic_cluster 0 on
 194                 chip cpu/amd/socket_940
 195                         device apic 0 on end
 196                 end
 197                 chip cpu/amd/socket_940
 198                         device apic 1 on end
 199                 end
 200         end
 201
 202         device pci_domain 0 on
 203                 chip northbridge/amd/amdk8
 204                         device pci 18.0 on end # LDT 0
 205                         device pci 18.0 on     # LDT 1
 206                                 chip southbridge/amd/amd8131
 207                                         device pci 0.0 on end
 208                                         device pci 0.1 on end
 209                                         device pci 1.0 on end
 210                                         device pci 1.1 on end
 211                                 end
 212                                 chip southbridge/amd/amd8111
 213                                         device pci 0.0 on
 214                                                 device pci 0.0 on end
 215                                                 device pci 0.1 on end
 216                                                 device pci 0.2 on end
 217                                                 device pci 1.0 on end
 218                                         end
 219                                         device pci 1.0 on
 220                                                 chip superio/winbond/w83627hf
 221                                                         device pnp 2e.0 on #  Floppy
 222                                                                 io 0x60 = 0x3f0
 223                                                                 irq 0x70 = 6
 224                                                                 drq 0x74 = 2
 225                                                         end
 226                                                         device pnp 2e.1 off #  Parallel Port
 227                                                                 io 0x60 = 0x378
 228                                                                 irq 0x70 = 7
 229                                                         end
 230                                                         device pnp 2e.2 on #  Com1
 231                                                                 io 0x60 = 0x3f8
 232                                                                 irq 0x70 = 4
 233                                                         end
 234                                                         device pnp 2e.3 on #  Com2
 235                                                                 io 0x60 = 0x2f8
 236                                                                 irq 0x70 = 3
 237                                                         end
 238                                                         device pnp 2e.5 on #  Keyboard
 239                                                                 io 0x60 = 0x60
 240                                                                 io 0x62 = 0x64
 241                                                                 irq 0x70 = 1
 242                                                                 irq 0x72 = 12
 243                                                         end
 244                                                         device pnp 2e.6 off #  CIR
 245                                                                 io 0x60 = 0x100
 246                                                         end
 247                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 248                                                                 io 0x60 = 0x220
 249                                                                 io 0x62 = 0x300
 250                                                                 irq 0x70 = 9
 251                                                         end
 252                                                         device pnp 2e.8 off end #  GPIO2
 253                                                         device pnp 2e.9 off end #  GPIO3
 254                                                         device pnp 2e.a off end #  ACPI
 255                                                         device pnp 2e.b on #  HW Monitor
 256                                                                 io 0x60 = 0x290
 257                                                                 irq 0x70 = 5
 258                                                         end
 259                                                 end
 260                                         end
 261                                         device pci 1.1 on end
 262                                         device pci 1.2 on end
 263                                         device pci 1.3 on end
 264                                         device pci 1.5 on end
 265                                         device pci 1.6 on end
 266                                 end
 267                         end # LDT1
 268                         device pci 18.0 on end # LDT2
 269                         device pci 18.1 on end
 270                         device pci 18.2 on end
 271                         device pci 18.3 on end
 272                 end
 273                 chip northbridge/amd/amdk8
 274                         device pci 19.0 on end
 275                         device pci 19.0 on end
 276                         device pci 19.0 on end
 277                         device pci 19.1 on end
 278                         device pci 19.2 on end
 279                         device pci 19.3 on end
 280                 end
 281         end
 282 end
 283