2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define FAM10_SCAN_PCI_BUS 0
28 #define FAM10_ALLOCATE_IO_RANGE 1
30 #define QRANK_DIMM_SUPPORT 1
32 #if CONFIG_LOGICAL_CPUS==1
33 #define SET_NB_CFG_54 1
36 #define FAM10_SET_FIDVID 1
37 #define FAM10_SET_FIDVID_CORE_RANGE 0
39 #define DBGP_DEFAULT 7
43 #include <device/pci_def.h>
44 #include <device/pci_ids.h>
46 #include <device/pnp_def.h>
47 #include <arch/romcc_io.h>
48 #include <cpu/x86/lapic.h>
49 #include "option_table.h"
50 #include "pc80/mc146818rtc_early.c"
51 #include "pc80/serial.c"
53 static void post_code(u8 value) {
57 #include "arch/i386/lib/console.c"
58 #if CONFIG_USBDEBUG_DIRECT
59 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
60 #include "pc80/usbdebug_direct_serial.c"
62 #include "lib/ramtest.c"
64 #include <cpu/amd/model_10xxx_rev.h>
66 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
67 #include "northbridge/amd/amdfam10/raminit.h"
68 #include "northbridge/amd/amdfam10/amdfam10.h"
70 #include "cpu/x86/lapic/boot_cpu.c"
71 #include "northbridge/amd/amdfam10/reset_test.c"
72 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
74 #include "cpu/x86/bist.h"
76 #include "northbridge/amd/amdfam10/debug.c"
78 #include "cpu/amd/mtrr/amd_earlymtrr.c"
80 #include "northbridge/amd/amdfam10/setup_resource_map.c"
82 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
83 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
85 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
87 static void memreset_setup(void)
91 static void memreset(int controllers, const struct mem_controller *ctrl)
95 static inline void activate_spd_rom(const struct mem_controller *ctrl)
100 static inline int spd_read_byte(unsigned device, unsigned address)
102 return smbus_read_byte(device, address);
105 #include "northbridge/amd/amdfam10/amdfam10.h"
106 #include "northbridge/amd/amdht/ht_wrapper.c"
108 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
109 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
110 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
112 #include "resourcemap.c"
114 #include "cpu/amd/quadcore/quadcore.c"
117 #define MCP55_USE_NIC 1
118 #define MCP55_USE_AZA 1
120 #define MCP55_PCI_E_X_0 1
122 #define MCP55_MB_SETUP \
123 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
124 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
125 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
126 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
127 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
128 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
130 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
131 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
133 #include "cpu/amd/car/copy_and_run.c"
135 #include "cpu/amd/car/post_cache_as_ram.c"
137 #include "cpu/amd/model_10xxx/init_cpus.c"
139 #include "cpu/amd/model_10xxx/fidvid.c"
141 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
142 #include "northbridge/amd/amdfam10/early_ht.c"
144 static void sio_setup(void)
150 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
152 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
154 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
156 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
159 #include "spd_addr.h"
160 #include "cpu/amd/microcode/microcode.c"
161 #include "cpu/amd/model_10xxx/update_microcode.c"
163 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
165 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
173 if (!cpu_init_detectedx && boot_cpu()) {
174 /* Nothing special needs to be done to find bus 0 */
175 /* Allow the HT devices to be found */
177 set_bsp_node_CHtExtNodeCfgEn();
178 enumerate_ht_chain();
182 /* Setup the mcp55 */
189 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
194 pnp_enter_ext_func_mode(SERIAL_DEV);
195 /* We have 24MHz input. */
196 reg = pnp_read_config(SERIAL_DEV, 0x24);
197 pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
198 pnp_exit_ext_func_mode(SERIAL_DEV);
200 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
205 /* Halt if there was a built in self test failure */
206 report_bist_failure(bist);
208 #if CONFIG_USBDEBUG_DIRECT
209 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
210 early_usbdebug_direct_init();
214 printk_debug("BSP Family_Model: %08x\n", val);
215 printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
216 printk_debug("bsp_apicid = %02x\n", bsp_apicid);
217 printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
219 /* Setup sysinfo defaults */
220 set_sysinfo_in_ram(0);
222 update_microcode(val);
228 amd_ht_init(sysinfo);
231 /* Setup nodes PCI space and start core 0 AP init. */
232 finalize_node_setup(sysinfo);
233 printk_debug("finalize_node_setup done\n");
235 /* Setup any mainboard PCI settings etc. */
236 printk_debug("setup_mb_resource_map begin\n");
237 setup_mb_resource_map();
238 printk_debug("setup_mb_resource_map end\n");
241 /* wait for all the APs core0 started by finalize_node_setup. */
242 /* FIXME: A bunch of cores are going to start output to serial at once.
243 * It would be nice to fixup prink spinlocks for ROM XIP mode.
244 * I think it could be done by putting the spinlock flag in the cache
245 * of the BSP located right after sysinfo.
247 wait_all_core0_started();
249 #if CONFIG_LOGICAL_CPUS==1
250 /* Core0 on each node is configured. Now setup any additional cores. */
251 printk_debug("start_other_cores()\n");
254 printk_debug("wait_all_other_cores_started()\n");
255 wait_all_other_cores_started(bsp_apicid);
260 #if FAM10_SET_FIDVID == 1
261 msr = rdmsr(0xc0010071);
262 printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
264 /* FIXME: The sb fid change may survive the warm reset and only
265 * need to be done once.*/
266 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
270 if (!warm_reset_detect(0)) { // BSP is node 0
271 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
273 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
278 /* show final fid and vid */
279 msr=rdmsr(0xc0010071);
280 printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
283 wants_reset = mcp55_early_setup_x();
285 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
286 if (!warm_reset_detect(0)) {
287 print_info("...WARM RESET...\n\n\n");
289 die("After soft_reset_x - shouldn't see this message!!!\n");
293 printk_debug("mcp55_early_setup_x wanted additional reset!\n");
297 /* It's the time to set ctrl in sysinfo now; */
298 printk_debug("fill_mem_ctrl()\n");
299 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
302 printk_debug("enable_smbus()\n");
309 printk_debug("raminit_amdmct()\n");
310 raminit_amdmct(sysinfo);
313 printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
314 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
315 post_code(0x43); // Should never see this post code.