2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
26 default CONFIG_XIP_ROM_SIZE = 64 * 1024
27 include /config/nofailovercalculation.lb
28 default CONFIG_ROM_PAYLOAD = 1
34 ## Build the objects we have code for in this directory.
39 #dir /drivers/ati/ragexl
40 #needed by irq_tables and mptable and acpi_tables
44 if CONFIG_HAVE_MP_TABLE object mptable.o end
45 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
58 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
60 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
67 ## Build our 16 bit and 32 bit coreboot entry code
69 if CONFIG_USE_FALLBACK_IMAGE
70 mainboardinit cpu/x86/16bit/entry16.inc
71 ldscript /cpu/x86/16bit/entry16.lds
74 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/32bit/entry32.lds
81 ldscript /cpu/amd/car/cache_as_ram.lds
85 ## Build our reset vector (This is where coreboot is entered)
87 if CONFIG_USE_FALLBACK_IMAGE
88 mainboardinit cpu/x86/16bit/reset16.inc
89 ldscript /cpu/x86/16bit/reset16.lds
91 mainboardinit cpu/x86/32bit/reset32.inc
92 ldscript /cpu/x86/32bit/reset32.lds
96 ## Include an id string (For safe flashing)
98 mainboardinit southbridge/nvidia/mcp55/id.inc
99 ldscript /southbridge/nvidia/mcp55/id.lds
102 ## ROMSTRAP table for MCP55
104 if CONFIG_USE_FALLBACK_IMAGE
105 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
106 ldscript /southbridge/nvidia/mcp55/romstrap.lds
110 ## Setup Cache-As-Ram
112 mainboardinit cpu/amd/car/cache_as_ram.inc
115 ### This is the early phase of coreboot startup
116 ### Things are delicate and we test to see if we should
117 ### failover to another image.
119 if CONFIG_USE_FALLBACK_IMAGE
120 ldscript /arch/i386/lib/failover.lds
124 ### O.k. We aren't just an intermediary anymore!
133 mainboardinit ./auto.inc
137 ## Include the secondary Configuration files
142 # sample config for msi/ms9282
143 chip northbridge/amd/amdk8/root_complex
144 device apic_cluster 0 on
145 chip cpu/amd/socket_F
150 device pci_domain 0 on
151 chip northbridge/amd/amdk8 #mc0
152 device pci 18.0 on # northbridge
153 # devices on link 0, link 0 == LDT 0
154 chip southbridge/nvidia/mcp55
155 device pci 0.0 on end # HT
156 device pci 1.0 on # LPC
157 chip superio/winbond/w83627ehg
158 device pnp 2e.0 on # Floppy
163 device pnp 2e.1 off # Parallel Port
167 device pnp 2e.2 on # Com1
171 device pnp 2e.3 off # Com2
175 device pnp 2e.5 on # Keyboard
181 device pnp 2e.6 off # SERIAL_FALSH
184 device pnp 2e.7 off # GAME_MIDI_GIPO1
189 device pnp 2e.8 off end # WDTO_PLED
190 device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
191 device pnp 2e.a off end # ACPI
192 device pnp 2e.b on # HW Monitor
198 device pci 1.1 on # SM 0
199 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
200 device i2c 70 on #0 pca9554 1
201 chip drivers/generic/generic #dimm 0-0-0
204 chip drivers/generic/generic #dimm 0-0-1
207 chip drivers/generic/generic #dimm 0-1-0
210 chip drivers/generic/generic #dimm 0-1-1
213 chip drivers/generic/generic #dimm 0-0-0
216 chip drivers/generic/generic #dimm 0-0-1
219 chip drivers/generic/generic #dimm 0-1-0
222 chip drivers/generic/generic #dimm 0-1-1
226 device i2c 70 on #0 pca9554 2
227 chip drivers/generic/generic #dimm 0-0-0
230 chip drivers/generic/generic #dimm 0-0-1
233 chip drivers/generic/generic #dimm 0-1-0
236 chip drivers/generic/generic #dimm 0-1-1
239 chip drivers/generic/generic #dimm 0-0-0
242 chip drivers/generic/generic #dimm 0-0-1
245 chip drivers/generic/generic #dimm 0-1-0
248 chip drivers/generic/generic #dimm 0-1-1
254 device pci 1.1 on # SM 1
255 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
256 device i2c 72 on #pca9554 channle1
257 chip drivers/i2c/adm1027 #HWM ADT7476 1
261 device i2c 72 on #pca9545 channel 2
262 chip drivers/i2c/adm1027 #HWM ADT7463
266 device i2c 72 on end #pca9545 channel 3
267 device i2c 72 on #pca9545 channel 4
268 chip drivers/i2c/adm1027 #HWM ADT7476 2
275 device pci 2.0 on end # USB 1.1
276 device pci 2.1 on end # USB 2
277 device pci 4.0 on end # IDE
278 device pci 5.0 on end # SATA 0
279 device pci 5.1 on end # SATA 1
280 device pci 5.2 on end # SATA 2
281 device pci 6.0 on #P2P
282 chip drivers/pci/onboard
283 device pci 4.0 on end
284 register "rom_address" = "0xfff80000"
287 device pci 7.0 on end # reserve
288 device pci 8.0 on end # MAC0
289 device pci 9.0 on end # MAC1
292 chip drivers/pci/onboard
293 device pci 4.0 on end #pci_E lan1
294 device pci 4.1 on end #pci_E lan2
298 device pci b.0 on end # PCI E 0x374
299 device pci c.0 on end
300 device pci d.0 on #SAS
301 chip drivers/pci/onboard
302 device pci 0.0 on end
305 device pci e.0 on end # PCI E 0 0x375
306 device pci f.0 on end #PCI E 0x377 pci_E slot
307 register "ide0_enable" = "1"
308 register "ide1_enable" = "1"
309 register "sata0_enable" = "1"
310 register "sata1_enable" = "1"
312 end # device pci 18.0
313 device pci 18.0 on end # Link 1
314 device pci 18.0 on end
315 device pci 18.1 on end
316 device pci 18.2 on end
317 device pci 18.3 on end
322 # chip drivers/generic/debug
323 # device pnp 0.0 off end
324 # device pnp 0.1 off end
325 # device pnp 0.2 off end
326 # device pnp 0.3 off end
327 # device pnp 0.4 off end
328 # device pnp 0.5 on end