src/mainboard/msi/ms9185/resourcemap.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2006 MSI
  10  * Written by bxshi <bingxunshi@gmail.com> for MSI.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  25  */
  26
  27 /*
  28  * ms9185  needs a different resource map
  29  *
  30  */
  31
  32 static void setup_ms9185_resource_map(void)
  33 {
  34        static const unsigned int register_values[] = {
  35                /* Careful set limit registers before base registers which contain the enables */
  36                /* DRAM Limit i Registers
  37                 * F1:0x44 i = 0
  38                 * F1:0x4C i = 1
  39                 * F1:0x54 i = 2
  40                 * F1:0x5C i = 3
  41                 * F1:0x64 i = 4
  42                 * F1:0x6C i = 5
  43                 * F1:0x74 i = 6
  44                 * F1:0x7C i = 7
  45                 * [ 2: 0] Destination Node ID
  46                 *         000 = Node 0
  47                 *         001 = Node 1
  48                 *         010 = Node 2
  49                 *         011 = Node 3
  50                 *         100 = Node 4
  51                 *         101 = Node 5
  52                 *         110 = Node 6
  53                 *         111 = Node 7
  54                 * [ 7: 3] Reserved
  55                 * [10: 8] Interleave select
  56                 *         specifies the values of A[14:12] to use with interleave enable.
  57                 * [15:11] Reserved
  58                 * [31:16] DRAM Limit Address i Bits 39-24
  59                 *         This field defines the upper address bits of a 40 bit  address
  60                 *         that define the end of the DRAM region.
  61                 */
  62                PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  63                PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  64                PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  65                PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  66                PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  67                PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  68                PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  69                PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  70                /* DRAM Base i Registers
  71                 * F1:0x40 i = 0
  72                 * F1:0x48 i = 1
  73                 * F1:0x50 i = 2
  74                 * F1:0x58 i = 3
  75                 * F1:0x60 i = 4
  76                 * F1:0x68 i = 5
  77                 * F1:0x70 i = 6
  78                 * F1:0x78 i = 7
  79                 * [ 0: 0] Read Enable
  80                 *         0 = Reads Disabled
  81                 *         1 = Reads Enabled
  82                 * [ 1: 1] Write Enable
  83                 *         0 = Writes Disabled
  84                 *         1 = Writes Enabled
  85                 * [ 7: 2] Reserved
  86                 * [10: 8] Interleave Enable
  87                 *         000 = No interleave
  88                 *         001 = Interleave on A[12] (2 nodes)
  89                 *         010 = reserved
  90                 *         011 = Interleave on A[12] and A[14] (4 nodes)
  91                 *         100 = reserved
  92                 *         101 = reserved
  93                 *         110 = reserved
  94                 *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  95                 * [15:11] Reserved
  96                 * [13:16] DRAM Base Address i Bits 39-24
  97                 *         This field defines the upper address bits of a 40-bit address
  98                 *         that define the start of the DRAM region.
  99                 */
 100                PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
 101                PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
 102                PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
 103                PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
 104                PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
 105                PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
 106                PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
 107                PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
 108
 109                /* Memory-Mapped I/O Limit i Registers
 110                 * F1:0x84 i = 0
 111                 * F1:0x8C i = 1
 112                 * F1:0x94 i = 2
 113                 * F1:0x9C i = 3
 114                 * F1:0xA4 i = 4
 115                 * F1:0xAC i = 5
 116                 * F1:0xB4 i = 6
 117                 * F1:0xBC i = 7
 118                 * [ 2: 0] Destination Node ID
 119                 *         000 = Node 0
 120                 *         001 = Node 1
 121                 *         010 = Node 2
 122                 *         011 = Node 3
 123                 *         100 = Node 4
 124                 *         101 = Node 5
 125                 *         110 = Node 6
 126                 *         111 = Node 7
 127                 * [ 3: 3] Reserved
 128                 * [ 5: 4] Destination Link ID
 129                 *         00 = Link 0
 130                 *         01 = Link 1
 131                 *         10 = Link 2
 132                 *         11 = Reserved
 133                 * [ 6: 6] Reserved
 134                 * [ 7: 7] Non-Posted
 135                 *         0 = CPU writes may be posted
 136                 *         1 = CPU writes must be non-posted
 137                 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 138                 *         This field defines the upp adddress bits of a 40-bit address that
 139                 *         defines the end of a memory-mapped I/O region n
 140                 */
 141                PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 142                PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 143                PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 144                PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 145                PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 146                PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 147                PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 148                PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
 149
 150                /* Memory-Mapped I/O Base i Registers
 151                 * F1:0x80 i = 0
 152                 * F1:0x88 i = 1
 153                 * F1:0x90 i = 2
 154                 * F1:0x98 i = 3
 155                 * F1:0xA0 i = 4
 156                 * F1:0xA8 i = 5
 157                 * F1:0xB0 i = 6
 158                 * F1:0xB8 i = 7
 159                 * [ 0: 0] Read Enable
 160                 *         0 = Reads disabled
 161                 *         1 = Reads Enabled
 162                 * [ 1: 1] Write Enable
 163                 *         0 = Writes disabled
 164                 *         1 = Writes Enabled
 165                 * [ 2: 2] Cpu Disable
 166                 *         0 = Cpu can use this I/O range
 167                 *         1 = Cpu requests do not use this I/O range
 168                 * [ 3: 3] Lock
 169                 *         0 = base/limit registers i are read/write
 170                 *         1 = base/limit registers i are read-only
 171                 * [ 7: 4] Reserved
 172                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 173                 *         This field defines the upper address bits of a 40bit address
 174                 *         that defines the start of memory-mapped I/O region i
 175                 */
 176                PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 177                PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 178                PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 179                PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 180                PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 181                PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 182                PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 183                PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 184
 185                /* PCI I/O Limit i Registers
 186                 * F1:0xC4 i = 0
 187                 * F1:0xCC i = 1
 188                 * F1:0xD4 i = 2
 189                 * F1:0xDC i = 3
 190                 * [ 2: 0] Destination Node ID
 191                 *         000 = Node 0
 192                 *         001 = Node 1
 193                 *         010 = Node 2
 194                 *         011 = Node 3
 195                 *         100 = Node 4
 196                 *         101 = Node 5
 197                 *         110 = Node 6
 198                 *         111 = Node 7
 199                 * [ 3: 3] Reserved
 200                 * [ 5: 4] Destination Link ID
 201                 *         00 = Link 0
 202                 *         01 = Link 1
 203                 *         10 = Link 2
 204                 *         11 = reserved
 205                 * [11: 6] Reserved
 206                 * [24:12] PCI I/O Limit Address i
 207                 *         This field defines the end of PCI I/O region n
 208                 * [31:25] Reserved
 209                 */
 210                PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
 211                PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 212                PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 213                PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 214
 215                /* PCI I/O Base i Registers
 216                 * F1:0xC0 i = 0
 217                 * F1:0xC8 i = 1
 218                 * F1:0xD0 i = 2
 219                 * F1:0xD8 i = 3
 220                 * [ 0: 0] Read Enable
 221                 *         0 = Reads Disabled
 222                 *         1 = Reads Enabled
 223                 * [ 1: 1] Write Enable
 224                 *         0 = Writes Disabled
 225                 *         1 = Writes Enabled
 226                 * [ 3: 2] Reserved
 227                 * [ 4: 4] VGA Enable
 228                 *         0 = VGA matches Disabled
 229                 *         1 = matches all address < 64K and where A[9:0] is in the
 230                 *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 231                 * [ 5: 5] ISA Enable
 232                 *         0 = ISA matches Disabled
 233                 *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 234                 *             from matching agains this base/limit pair
 235                 * [11: 6] Reserved
 236                 * [24:12] PCI I/O Base i
 237                 *         This field defines the start of PCI I/O region n
 238                 * [31:25] Reserved
 239                 */
 240                PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
 241                PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 242                PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 243                PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 244
 245                /* Config Base and Limit i Registers
 246                 * F1:0xE0 i = 0
 247                 * F1:0xE4 i = 1
 248                 * F1:0xE8 i = 2
 249                 * F1:0xEC i = 3
 250                 * [ 0: 0] Read Enable
 251                 *         0 = Reads Disabled
 252                 *         1 = Reads Enabled
 253                 * [ 1: 1] Write Enable
 254                 *         0 = Writes Disabled
 255                 *         1 = Writes Enabled
 256                 * [ 2: 2] Device Number Compare Enable
 257                 *         0 = The ranges are based on bus number
 258                 *         1 = The ranges are ranges of devices on bus 0
 259                 * [ 3: 3] Reserved
 260                 * [ 6: 4] Destination Node
 261                 *         000 = Node 0
 262                 *         001 = Node 1
 263                 *         010 = Node 2
 264                 *         011 = Node 3
 265                 *         100 = Node 4
 266                 *         101 = Node 5
 267                 *         110 = Node 6
 268                 *         111 = Node 7
 269                 * [ 7: 7] Reserved
 270                 * [ 9: 8] Destination Link
 271                 *         00 = Link 0
 272                 *         01 = Link 1
 273                 *         10 = Link 2
 274                 *         11 - Reserved
 275                 * [15:10] Reserved
 276                 * [23:16] Bus Number Base i
 277                 *         This field defines the lowest bus number in configuration region i
 278                 * [31:24] Bus Number Limit i
 279                 *         This field defines the highest bus number in configuration regin i
 280                 */
 281                PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
 282                PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 283                PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 284                PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 285        };
 286
 287        int max;
 288        max = ARRAY_SIZE(register_values);
 289        setup_resource_map(register_values, max);
 290 }
 291