2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
5 ## (Thanks to LSRA University of Mannheim for their support)
6 ## Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, write to the Free Software
20 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 uses CONFIG_HAVE_MP_TABLE
25 uses CONFIG_HAVE_PIRQ_TABLE
26 uses CONFIG_USE_FALLBACK_IMAGE
27 uses CONFIG_USE_FAILOVER_IMAGE
28 uses CONFIG_HAVE_FALLBACK_BOOT
29 uses CONFIG_HAVE_FAILOVER_BOOT
30 uses CONFIG_HAVE_HARD_RESET
31 uses CONFIG_IRQ_SLOT_COUNT
32 uses CONFIG_HAVE_OPTION_TABLE
34 uses CONFIG_MAX_PHYSICAL_CPUS
35 uses CONFIG_LOGICAL_CPUS
38 uses CONFIG_FALLBACK_SIZE
39 uses CONFIG_FAILOVER_SIZE
41 uses CONFIG_ROM_SECTION_SIZE
42 uses CONFIG_ROM_IMAGE_SIZE
43 uses CONFIG_ROM_SECTION_SIZE
44 uses CONFIG_ROM_SECTION_OFFSET
45 uses CONFIG_ROM_PAYLOAD
46 uses CONFIG_ROM_PAYLOAD_START
47 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
48 uses CONFIG_PAYLOAD_SIZE
50 uses CONFIG_XIP_ROM_SIZE
51 uses CONFIG_XIP_ROM_BASE
52 uses CONFIG_STACK_SIZE
54 uses CONFIG_USE_OPTION_TABLE
55 uses CONFIG_LB_CKS_RANGE_START
56 uses CONFIG_LB_CKS_RANGE_END
57 uses CONFIG_LB_CKS_LOC
58 uses CONFIG_MAINBOARD_PART_NUMBER
59 uses CONFIG_MAINBOARD_VENDOR
61 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
62 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
63 uses COREBOOT_EXTRA_VERSION
66 uses CONFIG_CROSS_COMPILE
70 uses CONFIG_TTYS0_BAUD
71 uses CONFIG_TTYS0_BASE
73 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
74 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
75 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
76 uses CONFIG_CONSOLE_SERIAL8250
77 uses CONFIG_CONSOLE_BTEXT
78 uses CONFIG_HAVE_INIT_TIMER
80 uses CONFIG_CONSOLE_VGA
81 uses CONFIG_PCI_ROM_RUN
82 uses CONFIG_HW_MEM_HOLE_SIZEK
84 uses CONFIG_USE_DCACHE_RAM
85 uses CONFIG_DCACHE_RAM_BASE
86 uses CONFIG_DCACHE_RAM_SIZE
88 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
89 uses CONFIG_AP_CODE_IN_CAR
90 uses CONFIG_USE_PRINTK_IN_CAR
91 uses CONFIG_MEM_TRAIN_SEQ
92 uses CONFIG_WAIT_BEFORE_CPUS_INIT
94 uses CONFIG_ENABLE_APIC_EXT_ID
95 uses CONFIG_APIC_ID_OFFSET
96 uses CONFIG_LIFT_BSP_APIC_ID
98 uses CONFIG_PCI_64BIT_PREF_MEM
100 uses CONFIG_HT_CHAIN_UNITID_BASE
101 uses CONFIG_HT_CHAIN_END_UNITID_BASE
102 uses CONFIG_SB_HT_CHAIN_ON_BUS0
103 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
105 uses CONFIG_LB_MEM_TOPK
108 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
110 default CONFIG_ROM_SIZE=(512*1024)
113 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
115 default CONFIG_FALLBACK_SIZE=(252*1024)
118 default CONFIG_FAILOVER_SIZE=(4*1024)
125 ## Build code for the fallback boot
127 default CONFIG_HAVE_FALLBACK_BOOT=1
128 default CONFIG_HAVE_FAILOVER_BOOT=1
131 ## Build code to reset the motherboard from coreboot
133 default CONFIG_HAVE_HARD_RESET=1
136 ## Build code to export a programmable irq routing table
138 default CONFIG_HAVE_PIRQ_TABLE=1
139 default CONFIG_IRQ_SLOT_COUNT=13
142 ## Build code to export an x86 MP table
143 ## Useful for specifying IRQ routing values
145 default CONFIG_HAVE_MP_TABLE=1
148 ## Build code to export a CMOS option table
150 default CONFIG_HAVE_OPTION_TABLE=1
153 ## Move the default coreboot cmos range off of AMD RTC registers
155 default CONFIG_LB_CKS_RANGE_START=49
156 default CONFIG_LB_CKS_RANGE_END=122
157 default CONFIG_LB_CKS_LOC=123
160 ## Build code for SMP support
161 ## Only worry about 2 micro processors
164 default CONFIG_MAX_CPUS=2
165 default CONFIG_MAX_PHYSICAL_CPUS=1
166 default CONFIG_LOGICAL_CPUS=1
169 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
171 ##HT Unit ID offset, default is 1, the typical one
172 default CONFIG_HT_CHAIN_UNITID_BASE=0
174 ##real SB Unit ID, default is 0x20, mean dont touch it at last
175 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x10
177 #make the SB HT chain on bus 0, default is not (0)
178 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
180 ##only offset for SB chain?, default is yes(1)
181 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
184 #default CONFIG_CONSOLE_BTEXT=1
187 default CONFIG_CONSOLE_VGA=1
188 default CONFIG_PCI_ROM_RUN=1
191 ## enable CACHE_AS_RAM specifics
193 default CONFIG_USE_DCACHE_RAM=1
194 #default CONFIG_DCACHE_RAM_BASE=0xcf000
195 #default CONFIG_DCACHE_RAM_SIZE=0x1000
196 default CONFIG_DCACHE_RAM_BASE=0xc8000
197 default CONFIG_DCACHE_RAM_SIZE=0x08000
198 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
199 default CONFIG_USE_INIT=0
201 default CONFIG_AP_CODE_IN_CAR=0
202 default CONFIG_MEM_TRAIN_SEQ=2
203 default CONFIG_WAIT_BEFORE_CPUS_INIT=0
206 #default CONFIG_ENABLE_APIC_EXT_ID=0
207 #default CONFIG_APIC_ID_OFFSET=0x10
208 #default CONFIG_LIFT_BSP_APIC_ID=0
211 #default CONFIG_PCI_64BIT_PREF_MEM=1
214 ## Build code to setup a generic IOAPIC
216 default CONFIG_IOAPIC=1
219 ## Clean up the motherboard id strings
221 default CONFIG_MAINBOARD_PART_NUMBER="K8N Neo3 (MS-7135)"
222 default CONFIG_MAINBOARD_VENDOR="MSI"
223 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
224 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x7135
227 ### coreboot layout values
230 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
231 default CONFIG_ROM_IMAGE_SIZE = (64*1024)
235 ## Use a small 8K stack
237 default CONFIG_STACK_SIZE=0x2000
240 ## Use a small 16K heap
242 default CONFIG_HEAP_SIZE=0x4000
245 ## Only use the option table in a normal image
247 #efault CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
248 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
251 ## coreboot C code runs at this location in RAM
253 default CONFIG_RAMBASE=0x00004000
256 ## Load the payload from the ROM
258 default CONFIG_ROM_PAYLOAD = 1
261 ### Defaults of options that you may want to override in the target config file
265 ## The default compiler
267 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
268 default CONFIG_HOSTCC="gcc"
271 ## Disable the gdb stub by default
273 default CONFIG_GDB_STUB=0
275 default CONFIG_USE_PRINTK_IN_CAR=1
278 ## The Serial Console
281 # To Enable the Serial Console
282 default CONFIG_CONSOLE_SERIAL8250=1
284 ## Select the serial console baud rate
285 default CONFIG_TTYS0_BAUD=115200
286 #default CONFIG_TTYS0_BAUD=57600
287 #default CONFIG_TTYS0_BAUD=38400
288 #default CONFIG_TTYS0_BAUD=19200
289 #default CONFIG_TTYS0_BAUD=9600
290 #default CONFIG_TTYS0_BAUD=4800
291 #default CONFIG_TTYS0_BAUD=2400
292 #default CONFIG_TTYS0_BAUD=1200
294 # Select the serial console base port
295 default CONFIG_TTYS0_BASE=0x3f8
297 # Select the serial protocol
298 # This defaults to 8 data bits, 1 stop bit, and no parity
299 default CONFIG_TTYS0_LCS=0x3
302 ### Select the coreboot loglevel
304 ## EMERG 1 system is unusable
305 ## ALERT 2 action must be taken immediately
306 ## CRIT 3 critical conditions
307 ## ERR 4 error conditions
308 ## WARNING 5 warning conditions
309 ## NOTICE 6 normal but significant condition
310 ## INFO 7 informational
311 ## CONFIG_DEBUG 8 debug-level messages
312 ## SPEW 9 Way too many details
314 ## Request this level of debugging output
315 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
316 ## At a maximum only compile in this level of debugging
317 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
320 ## Select power on after power fail setting
321 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
328 default CONFIG_CBFS=0