1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_HAVE_OPTION_TABLE
8 uses CONFIG_USE_OPTION_TABLE
9 uses CONFIG_ROM_PAYLOAD
10 uses CONFIG_IRQ_SLOT_COUNT
12 uses CONFIG_MAINBOARD_VENDOR
13 uses CONFIG_MAINBOARD_PART_NUMBER
14 uses COREBOOT_EXTRA_VERSION
16 uses CONFIG_FALLBACK_SIZE
17 uses CONFIG_STACK_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_IMAGE_SIZE
22 uses CONFIG_ROM_SECTION_SIZE
23 uses CONFIG_ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_PRECOMPRESSED_PAYLOAD
27 uses CONFIG_PAYLOAD_SIZE
30 uses CONFIG_XIP_ROM_SIZE
31 uses CONFIG_XIP_ROM_BASE
32 uses CONFIG_HAVE_MP_TABLE
33 uses CONFIG_CROSS_COMPILE
37 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
38 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
39 uses CONFIG_CONSOLE_SERIAL8250
40 uses CONFIG_TTYS0_BAUD
41 uses CONFIG_TTYS0_BASE
43 uses CONFIG_UDELAY_TSC
44 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
46 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
47 default CONFIG_ROM_SIZE = 256*1024
54 ## Build code for the fallback boot
56 default CONFIG_HAVE_FALLBACK_BOOT=1
61 default CONFIG_HAVE_MP_TABLE=0
64 ## Build code to reset the motherboard from coreboot
66 default CONFIG_HAVE_HARD_RESET=0
68 ## Delay timer options
70 default CONFIG_UDELAY_TSC=1
71 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
74 ## Build code to export a programmable irq routing table
76 default CONFIG_HAVE_PIRQ_TABLE=1
77 default CONFIG_IRQ_SLOT_COUNT=2
81 ## Build code to export a CMOS option table
83 default CONFIG_HAVE_OPTION_TABLE=0
86 ### coreboot layout values
89 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
90 default CONFIG_ROM_IMAGE_SIZE = 65536
91 default CONFIG_FALLBACK_SIZE = 131072
94 ## Use a small 8K stack
96 default CONFIG_STACK_SIZE=0x2000
99 ## Use a small 16K heap
101 default CONFIG_HEAP_SIZE=0x4000
104 ## Only use the option table in a normal image
106 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
107 default CONFIG_USE_OPTION_TABLE = 0
109 default CONFIG_RAMBASE = 0x00004000
111 default CONFIG_ROM_PAYLOAD = 1
114 ## The default compiler
116 default CONFIG_CROSS_COMPILE=""
117 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
118 default CONFIG_HOSTCC="gcc"
121 ## The Serial Console
124 # To Enable the Serial Console
125 default CONFIG_CONSOLE_SERIAL8250=1
127 ## Select the serial console baud rate
128 default CONFIG_TTYS0_BAUD=115200
129 #default CONFIG_TTYS0_BAUD=57600
130 #default CONFIG_TTYS0_BAUD=38400
131 #default CONFIG_TTYS0_BAUD=19200
132 #default CONFIG_TTYS0_BAUD=9600
133 #default CONFIG_TTYS0_BAUD=4800
134 #default CONFIG_TTYS0_BAUD=2400
135 #default CONFIG_TTYS0_BAUD=1200
137 # Select the serial console base port
138 default CONFIG_TTYS0_BASE=0x3f8
140 # Select the serial protocol
141 # This defaults to 8 data bits, 1 stop bit, and no parity
142 default CONFIG_TTYS0_LCS=0x3
145 ### Select the coreboot loglevel
147 ## EMERG 1 system is unusable
148 ## ALERT 2 action must be taken immediately
149 ## CRIT 3 critical conditions
150 ## ERR 4 error conditions
151 ## WARNING 5 warning conditions
152 ## NOTICE 6 normal but significant condition
153 ## INFO 7 informational
154 ## CONFIG_DEBUG 8 debug-level messages
155 ## SPEW 9 Way too many details
157 ## Request this level of debugging output
158 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
159 ## At a maximum only compile in this level of debugging
160 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
167 default CONFIG_CBFS=0