src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RAMINIT_SYSINFO 1
  22 #define SET_FIDVID 1
  23 #define QRANK_DIMM_SUPPORT 1
  24 #if CONFIG_LOGICAL_CPUS==1
  25 #define SET_NB_CFG_54 1
  26 #endif
  27
  28 #define RC0 (6<<8)
  29 #define RC1 (7<<8)
  30
  31 #define DIMM0 0x50
  32 #define DIMM1 0x51
  33
  34 #define SMBUS_HUB 0x71
  35
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <device/pci_def.h>
  39 #include <arch/io.h>
  40 #include <device/pnp_def.h>
  41 #include <arch/romcc_io.h>
  42 #include <cpu/x86/lapic.h>
  43 #include <pc80/mc146818rtc.h>
  44 #include <console/console.h>
  45
  46 #include <cpu/amd/model_fxx_rev.h>
  47 #include "northbridge/amd/amdk8/raminit.h"
  48 #include "cpu/amd/model_fxx/apic_timer.c"
  49 #include "lib/delay.c"
  50
  51 #include "cpu/x86/lapic/boot_cpu.c"
  52 #include "northbridge/amd/amdk8/reset_test.c"
  53 #include "northbridge/amd/amdk8/debug.c"
  54 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  55
  56 #include <usbdebug.h>
  57
  58 #include "cpu/x86/mtrr/earlymtrr.c"
  59 #include "cpu/x86/bist.h"
  60
  61 #include "northbridge/amd/amdk8/setup_resource_map.c"
  62
  63 #include "southbridge/amd/rs690/rs690_early_setup.c"
  64 #include "southbridge/amd/sb600/sb600_early_setup.c"
  65
  66 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69 }
  70
  71 /* called in raminit_f.c */
  72 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  73 {
  74 }
  75
  76 /*called in raminit_f.c */
  77 static inline int spd_read_byte(u32 device, u32 address)
  78 {
  79         return smbus_read_byte(device, address);
  80 }
  81
  82 #include "northbridge/amd/amdk8/amdk8.h"
  83 #include "northbridge/amd/amdk8/incoherent_ht.c"
  84 #include "northbridge/amd/amdk8/raminit_f.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "lib/generic_sdram.c"
  87 #include "resourcemap.c"
  88
  89 #include "cpu/amd/dualcore/dualcore.c"
  90
  91
  92 #include "cpu/amd/car/post_cache_as_ram.c"
  93
  94 #include "cpu/amd/model_fxx/init_cpus.c"
  95
  96 #include "cpu/amd/model_fxx/fidvid.c"
  97
  98 #include "northbridge/amd/amdk8/early_ht.c"
  99
 100 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 101 {
 102         device_t dev;
 103         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 104         int needs_reset = 0;
 105         u32 bsp_apicid = 0;
 106         msr_t msr;
 107         struct cpuid_result cpuid1;
 108         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 109
 110         if (!cpu_init_detectedx && boot_cpu()) {
 111                 /* Nothing special needs to be done to find bus 0 */
 112                 /* Allow the HT devices to be found */
 113                 enumerate_ht_chain();
 114
 115                 /* sb600_lpc_port80(); */
 116                 sb600_pci_port80();
 117         }
 118
 119         if (bist == 0) {
 120                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 121         }
 122
 123         enable_rs690_dev8();
 124         sb600_lpc_init();
 125
 126         dev=PNP_DEV(0x2e, W83627DHG_SP1);
 127         w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
 128         uart_init();
 129
 130 #if CONFIG_USBDEBUG
 131         sb600_enable_usbdebug(0);
 132         early_usbdebug_init();
 133 #endif
 134
 135         console_init();
 136
 137         /* Halt if there was a built in self test failure */
 138         report_bist_failure(bist);
 139         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 140
 141         setup_kt690_resource_map();
 142
 143         setup_coherent_ht_domain();
 144
 145 #if CONFIG_LOGICAL_CPUS==1
 146         /* It is said that we should start core1 after all core0 launched */
 147         wait_all_core0_started();
 148         start_other_cores();
 149 #endif
 150         wait_all_aps_started(bsp_apicid);
 151
 152         ht_setup_chains_x(sysinfo);
 153
 154         /* run _early_setup before soft-reset. */
 155         rs690_early_setup();
 156         sb600_early_setup();
 157
 158         /* Check to see if processor is capable of changing FIDVID  */
 159         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 160         cpuid1 = cpuid(0x80000007);
 161         if( (cpuid1.edx & 0x6) == 0x6 ) {
 162
 163                 /* Read FIDVID_STATUS */
 164                 msr=rdmsr(0xc0010042);
 165                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 166
 167                 enable_fid_change();
 168                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 169                 init_fidvid_bsp(bsp_apicid);
 170
 171                 /* show final fid and vid */
 172                 msr=rdmsr(0xc0010042);
 173                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 174
 175         } else {
 176                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 177                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 178         }
 179
 180         needs_reset = optimize_link_coherent_ht();
 181         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 182         rs690_htinit();
 183         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 184
 185         if (needs_reset) {
 186                 print_info("ht reset -\n");
 187                 soft_reset();
 188         }
 189
 190         allow_all_aps_stop(bsp_apicid);
 191
 192         /* It's the time to set ctrl now; */
 193         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 194                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 195         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 196         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 197
 198         rs690_before_pci_init();
 199         sb600_before_pci_init();
 200
 201         post_cache_as_ram();
 202 }
 203