2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <device/device.h>
22 #include <console/console.h>
23 #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
24 #include <x86emu/x86emu.h>
26 #include <pc80/mc146818rtc.h>
30 #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
31 static int int15_handler(void)
33 #define BOOT_DISPLAY_DEFAULT 0
34 #define BOOT_DISPLAY_CRT (1 << 0)
35 #define BOOT_DISPLAY_TV (1 << 1)
36 #define BOOT_DISPLAY_EFP (1 << 2)
37 #define BOOT_DISPLAY_LCD (1 << 3)
38 #define BOOT_DISPLAY_CRT2 (1 << 4)
39 #define BOOT_DISPLAY_TV2 (1 << 5)
40 #define BOOT_DISPLAY_EFP2 (1 << 6)
41 #define BOOT_DISPLAY_LCD2 (1 << 7)
43 printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
44 __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
47 case 0x5f35: /* Boot Display */
48 M.x86.R_AX = 0x005f; // Success
49 M.x86.R_CL = BOOT_DISPLAY_DEFAULT;
51 case 0x5f40: /* Boot Panel Type */
52 // M.x86.R_AX = 0x015f; // Supported but failed
53 M.x86.R_AX = 0x005f; // Success
54 M.x86.R_CL = 3; // Display ID
57 /* Interrupt was not handled */
61 /* Interrupt handled */
65 static void int15_install(void)
67 typedef int (* yabel_handleIntFunc)(void);
68 extern yabel_handleIntFunc yabel_intFuncArray[256];
69 yabel_intFuncArray[0x15] = int15_handler;
73 /* Hardware Monitor */
75 static u16 hwm_base = 0xa00;
77 static void hwm_write(u8 reg, u8 value)
79 outb(reg, hwm_base + 0x05);
80 outb(value, hwm_base + 0x06);
83 static void hwm_bank(u8 bank)
85 hwm_write(0x4e, bank);
88 #define FAN_CRUISE_CONTROL_DISABLED 0
89 #define FAN_CRUISE_CONTROL_SPEED 1
90 #define FAN_CRUISE_CONTROL_THERMAL 2
92 #define FAN_SPEED_5625 0
93 //#define FAN_TEMPERATURE_30DEGC 0
100 // FANIN Target Speed Register
101 // FANIN = 337500 / RPM
102 struct fan_speed fan_speeds[] = {
103 { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
104 { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
105 { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
106 { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
114 struct temperature temperatures[] = {
115 { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
116 { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
117 { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
118 { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
121 static void hwm_setup(void)
123 int cpufan_control = 0, sysfan_control = 0;
124 int cpufan_speed = 0, sysfan_speed = 0;
125 int cpufan_temperature = 0, sysfan_temperature = 0;
127 if (get_option(&cpufan_control, "cpufan_cruise_control") < 0)
128 cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
129 if (get_option(&cpufan_speed, "cpufan_speed") < 0)
130 cpufan_speed = FAN_SPEED_5625;
131 //if (get_option(&cpufan_temperature, "cpufan_temperature") < 0)
132 // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
134 if (get_option(&sysfan_control, "sysfan_cruise_control") < 0)
135 sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
136 if (get_option(&sysfan_speed, "sysfan_speed") < 0)
137 sysfan_speed = FAN_SPEED_5625;
138 //if (get_option(&sysfan_temperature, "sysfan_temperature") < 0)
139 // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
141 // hwm_write(0x31, 0x20); // AVCC high limit
142 // hwm_write(0x34, 0x06); // VIN2 low limit
145 hwm_write(0x59, 0x20); // Diode Selection
146 hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
149 hwm_write(0x54, 0xf1); // SYSTIN temperature offset
150 hwm_write(0x55, 0x19); // CPUTIN temperature offset
151 hwm_write(0x56, 0xfc); // AUXTIN temperature offset
153 hwm_bank(0x80); // Default
156 // 00 FANOUT is Manual Mode
157 // 01 FANOUT is Thermal Cruise Mode
158 // 10 FANOUT is Fan Speed Cruise Mode
159 switch (cpufan_control) {
160 case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
161 case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
163 switch (sysfan_control) {
164 case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
165 case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
167 // This register must be written first
168 hwm_write(0x04, fan_config);
170 switch (cpufan_control) {
171 case FAN_CRUISE_CONTROL_SPEED:
172 printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
173 fan_speeds[cpufan_speed].fan_speed);
174 hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
176 case FAN_CRUISE_CONTROL_THERMAL:
177 printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
178 temperatures[cpufan_temperature].deg_celsius,
179 temperatures[cpufan_temperature].deg_fahrenheit);
180 hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
184 switch (sysfan_control) {
185 case FAN_CRUISE_CONTROL_SPEED:
186 printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
187 fan_speeds[sysfan_speed].fan_speed);
188 hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
190 case FAN_CRUISE_CONTROL_THERMAL:
191 printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
192 temperatures[sysfan_temperature].deg_celsius,
193 temperatures[sysfan_temperature].deg_fahrenheit);
194 hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
198 hwm_write(0x0e, 0x02); // Fan Output Step Down Time
199 hwm_write(0x0f, 0x02); // Fan Output Step Up Time
201 hwm_write(0x47, 0xaf); // FAN divisor register
202 hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
204 hwm_write(0x40, 0x01); // Init, but no SMI#
209 extern u32 * cim_verb_data;
210 extern u32 cim_verb_data_size;
212 static void verb_setup(void)
214 // Default VERB is fine on this mainboard.
215 cim_verb_data = NULL;
216 cim_verb_data_size = 0;
219 // mainboard_enable is executed as first thing after
220 // enumerate_buses().
222 static void mainboard_enable(device_t dev)
224 #if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
225 /* Install custom int15 handler for VGA OPROM */
232 struct chip_operations mainboard_ops = {
233 CHIP_NAME("Kontron 986LCD-M Mainboard")
234 .enable_dev = mainboard_enable,