src/mainboard/iwill/dk8x/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   3
   4 #define SET_NB_CFG_54 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 //used by incoherent_ht
  10 //#define K8_ALLOCATE_IO_RANGE 1
  11
  12 //used by init_cpus and fidvid
  13 #define SET_FIDVID 0
  14 //if we want to wait for core1 done before DQS training, set it to 0
  15 #define SET_FIDVID_CORE0_ONLY 1
  16
  17 #if CONFIG_K8_REV_F_SUPPORT == 1
  18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  19 #endif
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include "option_table.h"
  30 #include "pc80/mc146818rtc_early.c"
  31
  32 #include <console/console.h>
  33 #include <cpu/amd/model_fxx_rev.h>
  34 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  35 #include "northbridge/amd/amdk8/raminit.h"
  36 #include "cpu/amd/model_fxx/apic_timer.c"
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40
  41 #include "cpu/x86/bist.h"
  42
  43 #include "lib/delay.c"
  44
  45 #include "northbridge/amd/amdk8/debug.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  52
  53 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  54
  55 /*
  56  * GPIO28 of 8111 will control H0_MEMRESET_L
  57  * GPIO29 of 8111 will control H1_MEMRESET_L
  58  */
  59 static void memreset_setup(void)
  60 {
  61         if (is_cpu_pre_c0()) {
  62                 /* Set the memreset low */
  63                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  64                 /* Ensure the BIOS has control of the memory lines */
  65                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  66         } else {
  67                 /* Ensure the CPU has controll of the memory lines */
  68                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  69         }
  70 }
  71
  72 static void memreset(int controllers, const struct mem_controller *ctrl)
  73 {
  74         if (is_cpu_pre_c0()) {
  75                 udelay(800);
  76                 /* Set memreset_high */
  77                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  78                 udelay(90);
  79         }
  80 }
  81
  82 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  83 {
  84 }
  85
  86 static inline int spd_read_byte(unsigned device, unsigned address)
  87 {
  88         return smbus_read_byte(device, address);
  89 }
  90
  91 #include "northbridge/amd/amdk8/amdk8.h"
  92 #include "northbridge/amd/amdk8/incoherent_ht.c"
  93 #include "northbridge/amd/amdk8/coherent_ht.c"
  94 #include "northbridge/amd/amdk8/raminit.c"
  95 #include "lib/generic_sdram.c"
  96 #include "lib/ramtest.c"
  97
  98  /* tyan does not want the default */
  99 #include "northbridge/amd/amdk8/resourcemap.c"
 100
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103 #define DIMM0 0x50
 104 #define DIMM1 0x51
 105 #define DIMM2 0x52
 106 #define DIMM3 0x53
 107 #define DIMM4 0x54
 108 #define DIMM5 0x55
 109 #define DIMM6 0x56
 110 #define DIMM7 0x57
 111
 112 #include "cpu/amd/car/post_cache_as_ram.c"
 113
 114 #include "cpu/amd/model_fxx/init_cpus.c"
 115
 116 #include "cpu/amd/model_fxx/fidvid.c"
 117
 118 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 119 #include "northbridge/amd/amdk8/early_ht.c"
 120
 121 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 122 {
 123         static const uint16_t spd_addr[] = {
 124                         // first node
 125                         DIMM0, DIMM2, 0, 0,
 126                         DIMM1, DIMM3, 0, 0,
 127
 128                         // second node
 129                         DIMM4, DIMM6, 0, 0,
 130                         DIMM5, DIMM7, 0, 0,
 131         };
 132
 133         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 134                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 135
 136         int needs_reset;
 137         unsigned bsp_apicid = 0;
 138
 139         if (!cpu_init_detectedx && boot_cpu()) {
 140                 /* Nothing special needs to be done to find bus 0 */
 141                 /* Allow the HT devices to be found */
 142
 143                 enumerate_ht_chain();
 144
 145                 /* Setup the rom access for 4M */
 146                 amd8111_enable_rom();
 147         }
 148
 149         if (bist == 0) {
 150                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 151         }
 152
 153         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 154         uart_init();
 155         console_init();
 156
 157         /* Halt if there was a built in self test failure */
 158         report_bist_failure(bist);
 159
 160         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 161
 162         setup_default_resource_map();
 163
 164         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 165
 166 #if CONFIG_MEM_TRAIN_SEQ == 1
 167         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 168 #endif
 169         setup_coherent_ht_domain(); // routing table and start other core0
 170
 171         wait_all_core0_started();
 172 #if CONFIG_LOGICAL_CPUS==1
 173         // It is said that we should start core1 after all core0 launched
 174         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 175          * So here need to make sure last core0 is started, esp for two way system,
 176          * (there may be apic id conflicts in that case)
 177          */
 178         start_other_cores();
 179         wait_all_other_cores_started(bsp_apicid);
 180 #endif
 181
 182         /* it will set up chains and store link pair for optimization later */
 183         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 184
 185 #if SET_FIDVID == 1
 186
 187         {
 188                 msr_t msr;
 189                 msr=rdmsr(0xc0010042);
 190                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 191
 192         }
 193
 194         enable_fid_change();
 195
 196         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 197
 198         init_fidvid_bsp(bsp_apicid);
 199
 200         // show final fid and vid
 201         {
 202                 msr_t msr;
 203                 msr=rdmsr(0xc0010042);
 204                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 205
 206         }
 207 #endif
 208
 209         needs_reset = optimize_link_coherent_ht();
 210         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 211
 212         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 213         if (needs_reset) {
 214                 print_info("ht reset -\n");
 215                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 216         }
 217
 218         allow_all_aps_stop(bsp_apicid);
 219
 220         //It's the time to set ctrl in sysinfo now;
 221         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 222
 223         enable_smbus();
 224
 225 #if 0
 226         dump_smbus_registers();
 227 #endif
 228
 229         memreset_setup();
 230
 231         //do we need apci timer, tsc...., only debug need it for better output
 232         /* all ap stopped? */
 233         init_timer(); // Need to use TMICT to synconize FID/VID
 234         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 235
 236 #if 0
 237         dump_pci_devices();
 238 #endif
 239
 240         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 241
 242 }
 243