3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_ROM_PAYLOAD_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
21 uses CONFIG_PRECOMPRESSED_PAYLOAD
29 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
35 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
36 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
37 uses COREBOOT_EXTRA_VERSION
42 uses DEFAULT_CONSOLE_LOGLEVEL
43 uses MAXIMUM_CONSOLE_LOGLEVEL
44 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
45 uses CONFIG_CONSOLE_SERIAL8250
57 ## ROM_SIZE is the size of boot ROM that this board will use.
58 default ROM_SIZE=524288
65 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
67 default FALLBACK_SIZE=131072
70 ## Build code for the fallback boot
72 default HAVE_FALLBACK_BOOT=1
75 ## Build code to reset the motherboard from coreboot
77 default HAVE_HARD_RESET=1
80 ## Build code to export a programmable irq routing table
82 default HAVE_PIRQ_TABLE=1
83 default IRQ_SLOT_COUNT=9
86 ## Build code to export an x86 MP table
87 ## Useful for specifying IRQ routing values
89 default HAVE_MP_TABLE=1
92 ## Build code to export a CMOS option table
94 default HAVE_OPTION_TABLE=1
97 ## Move the default coreboot cmos range off of AMD RTC registers
99 default LB_CKS_RANGE_START=49
100 default LB_CKS_RANGE_END=122
101 default LB_CKS_LOC=123
104 ## Build code for SMP support
105 ## Only worry about 2 micro processors
108 default CONFIG_MAX_CPUS=2
109 default CONFIG_MAX_PHYSICAL_CPUS=2
112 ## Build code to setup a generic IOAPIC
114 default CONFIG_IOAPIC=1
117 ## enable CACHE_AS_RAM specifics
119 default USE_DCACHE_RAM=1
120 default DCACHE_RAM_BASE=0xcf000
121 default DCACHE_RAM_SIZE=0x1000
122 default CONFIG_USE_INIT=0
125 ## Clean up the motherboard id strings
127 #default MAINBOARD_PART_NUMBER="HDAMA"
128 #default MAINBOARD_VENDOR="ARIMA"
129 #default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
130 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
133 ### coreboot layout values
136 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
137 default ROM_IMAGE_SIZE = 65536
140 ## Use a small 8K stack
142 default STACK_SIZE=0x2000
145 ## Use a small 16K heap
147 default HEAP_SIZE=0x4000
150 ## Only use the option table in a normal image
152 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
155 ## Coreboot C code runs at this location in RAM
157 default _RAMBASE=0x00004000
160 ## Load the payload from the ROM
162 default CONFIG_ROM_PAYLOAD = 1
165 ### Defaults of options that you may want to override in the target config file
169 ## The default compiler
171 #default CC="$(CROSS_COMPILE)gcc -m32"
172 #default HOSTCC="gcc"
175 ## Disable the gdb stub by default
177 default CONFIG_GDB_STUB=0
180 ## The Serial Console
183 # To Enable the Serial Console
184 default CONFIG_CONSOLE_SERIAL8250=1
186 ## Select the serial console baud rate
187 default TTYS0_BAUD=115200
188 #default TTYS0_BAUD=57600
189 #default TTYS0_BAUD=38400
190 #default TTYS0_BAUD=19200
191 #default TTYS0_BAUD=9600
192 #default TTYS0_BAUD=4800
193 #default TTYS0_BAUD=2400
194 #default TTYS0_BAUD=1200
196 # Select the serial console base port
197 default TTYS0_BASE=0x3f8
199 # Select the serial protocol
200 # This defaults to 8 data bits, 1 stop bit, and no parity
201 default TTYS0_LCS=0x3
204 ### Select the coreboot loglevel
206 ## EMERG 1 system is unusable
207 ## ALERT 2 action must be taken immediately
208 ## CRIT 3 critical conditions
209 ## ERR 4 error conditions
210 ## WARNING 5 warning conditions
211 ## NOTICE 6 normal but significant condition
212 ## INFO 7 informational
213 ## DEBUG 8 debug-level messages
214 ## SPEW 9 Way too many details
216 ## Request this level of debugging output
217 default DEFAULT_CONSOLE_LOGLEVEL=8
218 ## At a maximum only compile in this level of debugging
219 default MAXIMUM_CONSOLE_LOGLEVEL=8
222 ## Select power on after power fail setting
223 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"