1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
16 if CONFIG_HAVE_MP_TABLE object mptable.o end
17 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
23 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
24 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
30 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
31 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
32 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
33 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
39 ## Build our 16 bit and 32 bit coreboot entry code
41 if CONFIG_USE_FALLBACK_IMAGE
42 mainboardinit cpu/x86/16bit/entry16.inc
43 ldscript /cpu/x86/16bit/entry16.lds
46 mainboardinit cpu/x86/32bit/entry32.inc
49 ldscript /cpu/x86/32bit/entry32.lds
53 ldscript /cpu/amd/car/cache_as_ram.lds
57 ## Build our reset vector (This is where coreboot is entered)
59 if CONFIG_USE_FALLBACK_IMAGE
60 mainboardinit cpu/x86/16bit/reset16.inc
61 ldscript /cpu/x86/16bit/reset16.lds
63 mainboardinit cpu/x86/32bit/reset32.inc
64 ldscript /cpu/x86/32bit/reset32.lds
68 ## Include an id string (For safe flashing)
70 mainboardinit arch/i386/lib/id.inc
71 ldscript /arch/i386/lib/id.lds
76 mainboardinit cpu/amd/car/cache_as_ram.inc
79 ### This is the early phase of coreboot startup
80 ### Things are delicate and we test to see if we should
81 ### failover to another image.
83 if CONFIG_USE_FALLBACK_IMAGE
84 ldscript /arch/i386/lib/failover.lds
88 ### O.k. We aren't just an intermediary anymore!
97 mainboardinit ./auto.inc
101 ## Include the secondary Configuration files
105 chip northbridge/amd/amdk8/root_complex
106 device pci_domain 0 on
107 chip northbridge/amd/amdk8
108 device pci 18.0 on # northbridge
109 # devices on link 0, link 0 == LDT 0
110 chip southbridge/amd/amd8131
111 # the on/off keyword is mandatory
112 device pci 0.0 on end
113 device pci 0.1 on end
114 device pci 1.0 on end
115 device pci 1.1 on end
117 chip southbridge/amd/amd8111
118 # this "device pci 0.0" is the parent the next one
121 device pci 0.0 on end
122 device pci 0.1 on end
123 device pci 0.2 on end
124 device pci 1.0 off end
127 chip superio/winbond/w83627thf
128 device pnp 2e.0 on end
129 device pnp 2e.1 on end
130 device pnp 2e.2 on end
131 device pnp 2e.3 on end
132 device pnp 2e.4 on end
133 device pnp 2e.5 on end
134 device pnp 2e.6 on end
135 device pnp 2e.7 on end
136 device pnp 2e.8 on end
137 device pnp 2e.9 on end
138 device pnp 2e.a on end
141 device pci 1.1 on end
142 device pci 1.2 on end
143 device pci 1.3 on end
144 device pci 1.5 off end
145 device pci 1.6 off end
148 device pci 18.0 on end # LDT1
149 device pci 18.0 on end # LDT2
150 device pci 18.1 on end
151 device pci 18.2 on end
152 device pci 18.3 on end
154 chip northbridge/amd/amdk8
155 device pci 19.0 on end
156 device pci 19.0 on end
157 device pci 19.0 on end
158 device pci 19.1 on end
159 device pci 19.2 on end
160 device pci 19.3 on end
163 device apic_cluster 0 on
164 chip cpu/amd/socket_940
167 chip cpu/amd/socket_940