src/mainboard/iwill/dk8s2/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 ## ATI Rage XL framebuffering graphics driver
  51 dir /drivers/ati/ragexl
  52
  53 if USE_DCACHE_RAM
  54
  55 if CONFIG_USE_INIT
  56
  57 makerule ./auto.o
  58         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  59         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  60 end
  61
  62 else
  63
  64 makerule ./auto.inc
  65         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  66         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  67         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  68         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  69 end
  70
  71 end
  72 else
  73 ##
  74 ## Romcc output
  75 ##
  76 makerule ./failover.E
  77         depends "$(MAINBOARD)/failover.c ./romcc"
  78         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  79 end
  80
  81 makerule ./failover.inc
  82         depends "$(MAINBOARD)/failover.c ./romcc"
  83         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  84 end
  85
  86 makerule ./auto.E
  87         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  88         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  89 end
  90 makerule ./auto.inc
  91         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  92         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  93 end
  94
  95 end
  96
  97 ##
  98 ## Build our 16 bit and 32 bit coreboot entry code
  99 ##
 100 if USE_FALLBACK_IMAGE
 101         mainboardinit cpu/x86/16bit/entry16.inc
 102         ldscript /cpu/x86/16bit/entry16.lds
 103 end
 104
 105 mainboardinit cpu/x86/32bit/entry32.inc
 106
 107 if USE_DCACHE_RAM
 108         if CONFIG_USE_INIT
 109                 ldscript /cpu/x86/32bit/entry32.lds
 110         end
 111
 112         if CONFIG_USE_INIT
 113                 ldscript      /cpu/amd/car/cache_as_ram.lds
 114         end
 115 end
 116
 117 ##
 118 ## Build our reset vector (This is where coreboot is entered)
 119 ##
 120 if USE_FALLBACK_IMAGE
 121         mainboardinit cpu/x86/16bit/reset16.inc
 122         ldscript /cpu/x86/16bit/reset16.lds
 123 else
 124         mainboardinit cpu/x86/32bit/reset32.inc
 125         ldscript /cpu/x86/32bit/reset32.lds
 126 end
 127
 128 if USE_DCACHE_RAM
 129 else
 130 ### Should this be in the northbridge code?
 131 mainboardinit arch/i386/lib/cpu_reset.inc
 132 end
 133
 134 ##
 135 ## Include an id string (For safe flashing)
 136 ##
 137 mainboardinit arch/i386/lib/id.inc
 138 ldscript /arch/i386/lib/id.lds
 139
 140 if USE_DCACHE_RAM
 141 ##
 142 ## Setup Cache-As-Ram
 143 ##
 144 mainboardinit cpu/amd/car/cache_as_ram.inc
 145 end
 146
 147 ###
 148 ### This is the early phase of coreboot startup
 149 ### Things are delicate and we test to see if we should
 150 ### failover to another image.
 151 ###
 152 if USE_FALLBACK_IMAGE
 153 if USE_DCACHE_RAM
 154        ldscript /arch/i386/lib/failover.lds
 155 else
 156        ldscript /arch/i386/lib/failover.lds
 157         mainboardinit ./failover.inc
 158 end
 159 end
 160
 161 ###
 162 ### O.k. We aren't just an intermediary anymore!
 163 ###
 164
 165 ##
 166 ## Setup RAM
 167 ##
 168 if USE_DCACHE_RAM
 169
 170 if CONFIG_USE_INIT
 171 initobject auto.o
 172 else
 173 mainboardinit ./auto.inc
 174 end
 175
 176 else
 177
 178 ##
 179 ## Setup RAM
 180 ##
 181 mainboardinit cpu/x86/fpu/enable_fpu.inc
 182 mainboardinit cpu/x86/mmx/enable_mmx.inc
 183 mainboardinit cpu/x86/sse/enable_sse.inc
 184 mainboardinit ./auto.inc
 185 mainboardinit cpu/x86/sse/disable_sse.inc
 186 mainboardinit cpu/x86/mmx/disable_mmx.inc
 187 end
 188
 189 ##
 190 ## Include the secondary Configuration files
 191 ##
 192 config chip.h
 193
 194 # config for iwill/dk8s2
 195 chip northbridge/amd/amdk8/root_complex
 196         device pci_domain 0 on
 197                 chip northbridge/amd/amdk8
 198                         device pci 18.0 on # LDT 0
 199                                 chip southbridge/amd/amd8131
 200                                         device pci 0.0 on end
 201                                         device pci 0.1 on end
 202                                         device pci 1.0 on end
 203                                         device pci 1.1 on end
 204                                 end
 205                                 chip southbridge/amd/amd8111
 206                                         # this "device pci 0.0" is the parent the next one
 207                                         # PCI bridge
 208                                         device pci 0.0 on
 209                                                 device pci 0.0 on end
 210                                                 device pci 0.1 on end
 211                                                 device pci 0.2 on end
 212                                                 device pci 1.0 off end
 213                                         end
 214                                         device pci 1.0 on
 215                                                 chip superio/winbond/w83627hf
 216                                                         device pnp  2e.0 on      # Floppy
 217                                                                  io 0x60 = 0x3f0
 218                                                                 irq 0x70 = 6
 219                                                                 drq 0x74 = 2
 220                                                         end
 221                                                         device pnp  2e.1 off     # Parallel Port
 222                                                                  io 0x60 = 0x378
 223                                                                 irq 0x70 = 7
 224                                                         end
 225                                                         device pnp  2e.2 on      # Com1
 226                                                                  io 0x60 = 0x3f8
 227                                                                 irq 0x70 = 4
 228                                                         end
 229                                                         device pnp  2e.3 off     # Com2
 230                                                                 io 0x60 = 0x2f8
 231                                                                 irq 0x70 = 3
 232                                                         end
 233                                                         device pnp  2e.5 on      # Keyboard
 234                                                                  io 0x60 = 0x60
 235                                                                  io 0x62 = 0x64
 236                                                                irq 0x70 = 1
 237                                                                 irq 0x72 = 12
 238                                                         end
 239                                                         device pnp  2e.6 off end # CIR
 240                                                         device pnp  2e.7 off end # GAME_MIDI_GIPO1
 241                                                         device pnp  2e.8 off end # GPIO2
 242                                                         device pnp  2e.9 off end # GPIO3
 243                                                         device pnp  2e.a off end # ACPI
 244                                                         device pnp  2e.b on      # HW Monitor
 245                                                                  io 0x60 = 0x290
 246                                                         end
 247                                                         register "com1" = "{1}"
 248                                                 #       register "com1" = "{1, 0, 0x3f8, 4}"
 249                                                 #       register "lpt" = "{1}"
 250                                                 end
 251                                         end
 252                                         device pci 1.1 on end
 253                                         device pci 1.2 on end
 254                                         device pci 1.3 on end
 255                                         device pci 1.5 off end
 256                                         device pci 1.6 off end
 257                                 end
 258                         end # LDT0
 259                         device pci 18.0 on end # LDT1
 260                         device pci 18.0 on end # LDT2
 261                         device pci 18.1 on end
 262                         device pci 18.2 on end
 263                         device pci 18.3 on end
 264                 end
 265                 chip northbridge/amd/amdk8
 266                         device pci 19.0 on end
 267                         device pci 19.0 on end
 268                         device pci 19.0 on end
 269                         device pci 19.1 on end
 270                         device pci 19.2 on end
 271                         device pci 19.3 on end
 272                 end
 273         end
 274         device apic_cluster 0 on
 275                 chip cpu/amd/socket_940
 276                         device apic 0 on end
 277                 end
 278                 chip cpu/amd/socket_940
 279                         device apic 1 on end
 280                 end
 281         end
 282 end
 283