1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
10 #include <cpu/amd/amdk8_sysconf.h>
11 #include "mb_sysconf.h"
13 static void *smp_write_config_table(void *v)
15 struct mp_config_table *mc;
16 unsigned char bus_num;
18 struct mb_sysconf_t *m;
20 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
22 mptable_init(mc, "DK8-HTX ", LAPIC_ADDR);
24 smp_write_processors(mc);
31 /* define bus and isa numbers */
32 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
33 smp_write_bus(mc, bus_num, "PCI ");
35 smp_write_bus(mc, m->bus_isa, "ISA ");
37 /*I/O APICs: APIC ID Version State Address*/
38 smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
42 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
44 res = find_resource(dev, PCI_BASE_ADDRESS_0);
46 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
49 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
51 res = find_resource(dev, PCI_BASE_ADDRESS_0);
53 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
59 for(i=1; i< sysconf.hc_possible_num; i++) {
60 if(!(sysconf.pci1234[i] & 0x1) ) continue;
62 switch(sysconf.hcid[i]) {
65 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
67 res = find_resource(dev, PCI_BASE_ADDRESS_0);
69 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
72 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
74 res = find_resource(dev, PCI_BASE_ADDRESS_0);
76 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
86 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
89 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
95 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
104 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
108 //Slot 2 PCI-X 133/100/66
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
113 //Slot 3 PCI-X 133/100/66
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
118 //Slot 4 PCI-X 133/100/66
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
132 for(i=1; i< sysconf.hc_possible_num; i++) {
133 if(!(sysconf.pci1234[i] & 0x1) ) continue;
136 struct resource *res;
137 switch(sysconf.hcid[i]) {
140 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
142 res = find_resource(dev, PCI_BASE_ADDRESS_0);
144 //Slot 1 PCI-X 133/100/66
145 for(ii=0;ii<4;ii++) {
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
151 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
153 res = find_resource(dev, PCI_BASE_ADDRESS_0);
155 //Slot 2 PCI-X 133/100/66
156 for(ii=0;ii<4;ii++) {
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
175 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
176 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
177 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
178 /* There is no extension information... */
180 /* Compute the checksums */
181 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
182 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
183 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
184 mc, smp_next_mpe_entry(mc));
185 return smp_next_mpe_entry(mc);
188 unsigned long write_smp_table(unsigned long addr)
191 v = smp_write_floating_table(addr);
192 return (unsigned long)smp_write_config_table(v);